No, I am not trolling. I am not sealioning. I might be specially pleading - I am not sure.
Segfault has been 'proven'. VME was proven and fixed - but there are still examples of people that can't get the old stuff to run on Win98 on Ryzen (with SVM enabled, other VMs work fine), but the exact...
Basically my point is that these errata appeared a little (maybe a lot) more serious and pervasive than normal to me. I remember the Sandy Bridge chipset recall, Atoms self-bricking and Phenom issues as the several 'big' examples of modern arches having serious hard-to-fix issues. If you patch...
Basically it is that while things may appear alright on the surface for those millions, could the bulk of the iceberg be underneath the waves? Especially with nondeterministic stuff like the cause of segfault - could BSOD this or that be a hardware issue rather than a software one? (But be...
Segfault was apparently a manufacturing issue of some kind. AMD reps have basically confirmed there is no microcode fix for that issue (though updated GCC may not hit the processor the right way to cause it), and it does not occur on older AMD or Intel systems. There is a RMA process setup for...
I'm sure many of us here have vague memories of chips that had real-world, unfixable bugs and problems. Problems that would not go away with a better motherboard, BIOS updates, OS reinstalls - without rewritten software. Problems that others might even blame on a bad overclock until the OP...
As has been said many times on this thread, just because there are two possibilities doesn't necessarily mean that both are equally likely. I either wake up a billionaire tomorrow or I don't, but does anyone here think that it's a 50-50 chance between the two?
Only 1 of two boxes remains. However, it's more likely that the first golden ball you chose was in the first box.
While you did choose a box at random, any time you chose Box 2 but pulled silver the first try, you lost the first go. So only half the time you pulled the first ball in Box 2, was...
I think a lot of people here do not realise that while you are indeed drawing the 2nd ball from the same box as the first (gold) one...
It is more likely (2/3) that the (gold) ball you chose first was in the first box, and hence there is a 2/3 chance you 'chose the first box'.
Which...
Literally happened to me. Hopefully it was just a bad UEFI update from MS, but the symptoms it produced were disconcerting ie. PC sometimes booting, then suddenly shutting off, or refusing to allow me to change settings by shutting off if I tried:
(This would imply active malware or...
This would be very much like Midgard. Sequentially executed, but pipelined and speculatively executed to increase serial performance, using a heuristic engine or just plain 'try every possibility!!!' for the simple predictable code. The differences are: it's x86, there's no RISC decode because...
Simple. 40x comes from the extreme density of the various native x86 instructions
Intel and AMD RISC dynarecs are power hungry and inefficient compared to this, with way lower IPC. As to why 'nobody else has ever thought of this before': that's not true. Many people have thought of elements of...
Because they would be given the opportunity to make a lot of money from this design by working together. If they don't, we flat-out refuse to share any SystemVerilog and process node IP with them, and pit them against each other until one cracks and agrees to do the 1486, while the other misses...
Main technical, financial, legal and corporate details.
Intel will be forced into a brutal, no-holds-barred patent war if they attempt to sue over x86 licensing for this and they will be fought to the last dollar.
I've been very heavily involved in the overall architecture of this project and...
.......................................
No selling outside of the FS/T forum.
Also no selling of items not in your possession.
esquared
Anandtech Forum Director
The design is being prototyped as we speak.
300mm high volume production will most likely exist by Q1 2021.
Can't remember where/when I thought this was actually happening... no solid evidence.
I apologise, it's been an exhausting 4 months.
(Edited)
The mid-2000s AMD GPUs were hardwired VLIW and enjoyed moderate success. The Elbrus 2000 and its derivatives have also had limited success in Russia for national security reasons.
IBM POWER and various SPARC CPUs could be said to be VLIW in the way they input and output data over their buses.
I see potential solutions to this problem: Break the CPU die (for an 8-core design like this on 14nm FinFET: ~600-900mm^2) up into much smaller die. These smaller die implement the logic but are much cheaper to manufacture and have a much higher yield. Perhaps even move a lot of the DDR5 memory...
So, I've been doing a fair bit of work on this. Excerpts:
http://forum.6502.org/viewtopic.php?f=4&t=5033
https://www.reddit.com/r/Amd/comments/7yhtuc/tsmc_samsung_and_globalfoundries_have_overtaken/dujczm9/
Might be Windows caching things on the drive. You can disable this by right clicking on the drive in Windows Explorer > Properties > click on the Hardware tab > Click on the drive you want > Properties > Change Settings > Policies > see if any of the two options here are enabled.
Thoughts? With modern transistor budgets, could a hardware dynarec be added to the old Elbrus 2000 architecture to eliminate the old argument of 'you need software optimisation for VLIW to work'? Thus, you have a 'pure CISC' x86 CPU gobbling up massive CISC instructions in one fell swoop, and...
I think the question will be: will there be enough of a density improvement and economic incentive for Seagate to do it and drive farms to buy said drives? I suspect the answer is no for the near future, personally.
Grounding problem/standoff mounting issue, perhaps? And yeah, PSU sounds like a likely culprit, if there's any way you can scavenge another one to test.
Perhaps buy an identical SD card from the same manufacturer, crack it open... swap guts if possible? (again taking into account what Elixer said above)
Well the thing with filling up a HDD to max is that the R/W head is moving towards the centre of the platter and thus the circumference of the region it's flying round gets smaller and smaller as the HDD continues to fill up. The head's flying over less sectors = less data flown over per second...
What the guy above said. Bad sectors take a long time to error-correct AND the drive must remap it, meaning the read/write head must move to a different location (SLOW).
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.