It is not just Apple but all ARM64 SoCs - because the raytracing kernel is implemented using the Intel Embree library, which uses SSE/AVX SIMD implementation to speed-up computation. Issue is, that the ARM64 implementation is just a simple SSE-2-NEON wrapper. So technically the implementation is...
If this is a phone chip it will have around 4W TDP - 12W are far from being sustainable in a phone chassis. I am talking about sustained performance and not short term peak.
Look at a random Laptop with Intel CPU, there is a big gap between PL1 and PL2. PL1 is the relevant metric here, as that...
Currently the medium cores are only loaded if I need full multicore performance. For background tasks I barely see them taking more than 20% load.
So background tasks can not possibly the argument for adding more medium cores - and yes I am talking Windows here.
However in a thermally...
Static power of SRAM is highly dependent on the minimum cycle time. So lower clocked LLC has much less leakage per MByte than say L1$ - we are talking factors here.
In general you save power when avoiding expensive DRAM access.
I am not sure, if the Snapdragon 850 is fully compatible with Hyper-V (e.g. for Linux/WSL). On the other hand, with 4GByte memory, trying WSL or WSA (Android) is most likely pointless.
It is crazy, that you are getting LTE with these models.
Excuse my ignorance, but the Qualcomm 8CX Gen 3 is extremely competitive against any 9W and below SoC from Intel or AMD - including those Jasper Lake and Lakemont based SoCs discussed right here.
Few comments. The cubic scaling only holds locally, because the F/V curve is not linear - it is rather a hyperbolic function, which has a zero/pole roughly at Vth. This means at half the frequency you might need more or less than half the voltage - depending on what your reference point is...
Depends on how you see it. Despite the article being 4 years old, most of the things stated there still hold true. That shows you how slow things are moving and that a decade is already underestimated.
In fact as was pointed out, the window of opportunity might be closing for RISC-V, as there is...
A backup plan based on a ground up design does not really help. It could be a ground-up design today already. As you correctly are pointing out, the only thing that matters is, what the judge believe it is. The proof needs to be presented by ARM and some evidence is most likely not sufficient...
You are dreaming of some non-existing cores. The topic is about P670, which does not even match the integer performance of Cortex A-78. Perhaps some very low-end devices, which suffer even more under dynarec.
Box64 is only available as dynarec for x64/x86->ARM64. Everything else is...
You probably missed the memo, that Qualcomms compute platforms only contain X- and 7-series cores since 2021. It probably beat the Qualcomm compute platforms from 2018 - but who cares. And this is before we are talking about ARM64 and x64 emulation, which would be required for both Android and...
Currently the lawsuit has no direct impact to engineering and only limited impact to marketing. Whatever they develop under the Qualcomm ALA, they are allowed to do so. The dispute is about the old Nuvia IP.
The positions are not really apart. The only open question is, if Qualcomm has destroyed the Nuvia IP or not. Qualcomm claims yes, but ARM says they have evidence that it is not destroyed. Of course ARM can not really prove this without insider knowledge.
And most likely there are some...
Make no mistake, the Cortex-X3 is already very close to the Apple core IPC wise. A quick calculation based on the Cortex X1 give the following picture:
Geekbench 5.4 ST for X1 @ 3GHz: 1250
X1 -> X3 (25%) = 1562
X3@3GHz -> X3@3.6GHz = 1875
Thats close to M2.
The reason ARMs claims are weak is, that Qualcomm is in the situation to re-create the Nuvia IP after they destroyed it - they did hire the people who designed the Nuvia cores. The whole lawsuit centers around the claim, that Qualcomm (according to ARM) did not have enough time to re-create the...
The problem of course is, that notebookcheck does not really do a SoC analysis. They compare the 2 SoCs at different voltages - which is totally pointless when you want to reason about the efficiency of the SoC.
That having said, the M2 could (and most likely is) more efficient than the M1 at...
The 8CX Gen 3 devices like the Lenovo Thinkpad X13s and the Surface Pro 9 SQ3 are Windows laptops, are fan-less with a 9W TDP similar to the M1 Air with about 16% less performance - so the distance is relatively small on the efficiency side. The efficiency loss can be explained by the fact that...
The small cores are already gone for laptop chips like the 8CX Gen 3 - where only large and medium cores are used - similar to Apple. Going below the 7 series like the Cortex A78 for medium cores is pointless for laptops.
This statement does not seem coming from experience. The vast majority of issues, which lead to additional steppings could have been found by RTL simulation. As I explained in my previous post, it is largely a coverage problem not an inherent problem of the simulation of digital circuits.
I...
Sure, there is RTL and gate level simulation available for design verification. However the coverage on system level typically is very low for various reasons - one is simulation speed (10^6 times slower than real-time or even less).
Right, the installer typically figures out the target architecture. On the other hand, there are no desktop class ARM SoCs available today. The fastest ARM SoC for Windows (if we exclude the server class machines), which is the 8CX Gen 3, is still a 9-10W TDP design for fan-less portables. The...
The problem you neglect is, that the major difference between Linux and RISC-V is, that in case of RISC-V only the ISA is free but not necessarily the implementations. In case of Linux the interfaces AND the implementation is free. As example, SiFive is not openly disclosing the implementations...
Thats what we are doing, we forked the toolchain because we are adding custom extensions to our RISC-V cores. However that is what everyone else doing as well in the microcontroller/embedded space.
Not sure what you are talking about. You can build and run ARM64 builds of Haiku OS right now, while on RISC-V only parts of the bootloader works. You are right, the ARM64 build still has lots of issues but its far more advanced than the RISC-V build.
You overestimate the impact of the ISA used during study. Since ages it typically has been MIPS. In any case, whatever you learn has much more generalized application outside of the sample ISA used.
It is in the filing. In any case what Softbank tries to claim is, that the IP in upcoming products is in fact the Nuvia IP, which was developed under the Nuvia license years ago. They are trying to support their claims by quoting Qualcomm press releases, where Qualcomm used the word "Nuvia" to...
Qualcomm did confirm that the Nuvia IP has been destroyed. They are developing cores under their own license - there was no need to transfer the Nuvia license - and Qualcomm did not ask to transfer the license either. Softbank is well aware that they have zero chance of winning this, but they...
Finally a well reasoned statement! Nuvia guys went to Qualcomm to work on PC/Phones CPUs and Qualcomm has indeed such a license. I does not really matter on what potential products Nuvia worked before with their Server License. Indeed sounds to me as Softbank tries make some quick money.
Agreed. Just giving an example: In case of the Intel Embree library (used by Cinebench for instance) it is just a static mapper of each AVX/SSE intrinsic to a set of NEON intrinsics.
Whatever you compare, the IPC gains of ARM are larger over the last 2 years, than Apples - in fact Apples IPC gains are single digit.
If the device manufacturers are doing reasonable decision with respect to choice of cores is another question. It could very well be, that for Phones going with 6...
That is consistent, when you read the fine-print. The 22% includes a 10% frequency uplift. Its +11% IPC and +10% frequency - they essentially compare devices clocked 10% higher.
We compare the fastest cores if you are interested in "catch-up'. What the device manufacturers integrate is up to them - DSU-110 allows 8 X-cores. Also 8CX Gen 3 integrates 4 X cores.
Not sure, what ARM is trying relative to Apple, as their design goals are different - however they are de-facto catching up to Apple, as ARMs IPC uplift has been greater than Apples over the last 2 years. Apple did not have anywhere close to 30% IPC uplift over the last 2 years.
I wonder what...
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