They're all using Clang/LLVM of similar versions (and please do not now tell me because the subversions aren't the same it's not valid).
Again, all documented over the various articles over time: https://images.anandtech.com/doci/15603/SPEC-April2020.png
NO JUST NO. The EPYC I/O die design is literally just a quadrupled desktop I/O die - AMD even officially stated this and touted this as a design advantage. You can literally see it in the die shot. I even covered this in articles...
You should be ashamed to call yourself a moderator here. You're calling a troll one of the actual people designing these chips - it's utter insanity.
Edit: To moderators: Then ban me already. The fact that a moderator is openly trolling here in this forum while adorning a big yellow Super...
The problem is that you're presenting a theory based on the RISC vs CISC argument that keep have been bringing up to the IPC argument, which hasn't been valid for over a decade and certainly not valid for AArch64. It *is* the same stupid old argument that just needs to outright die instead of...
I'm not even going to read your whole post because it's the same old stupid IPC story which is just wrong with absolutely no tether to reality. The whole CISC vs RISC thing being brought up is akin to no technical knowledge on the topic.
(For those people understanding the topic know the...
It's wide-ish on paper but falls apart on some regards, stuff like dispatch width is still 50% narrower than Apple. The design was botched in the M3 and they never recovered.
Apple does get 83% more IPC. Please don't spread technical nonsense which can be disproved easily by things such as performance counters. Bolding such false statements also isn't a good image from a CPU forum moderator.
Moderator call-outs are not allowed.
If you have an issue with a...
Hahaha what!!. The Switch is down-clocked because otherwise the X1 would melt a hole in it and battery would last 1-2 hours. At full power it's 7W GPU only for like a 13-14W SoC on a 3D workload. Why the heck do you think the Switch is actively cooled while phones are passive? Phone SoCs are far...
None of these benchmarks are even explicitly targeting the specific CPU microarchitecture, just the target ISA. If your background is compiler work then I hope you can differentiate between a compiler's front-end and back-end. Your previous big post is just a huge pile of nonsense, full of...
It's completely useless in client workloads. As I explain in the article, the only gains are in data-plane workloads in which the work data is accessed at higher latency; i.e. server and cloud environments. Marvell very much said it themselves in their briefing that higher compute workloads...
This is not the place here in the CPU forum but wow talk about pulling figures out of your ass on such a topic? The confirmed cases are at 17660 with 1266 deaths, resulting in a 7% death rate, and you know there's tons more unconfirmed infected, bringing down the real percentage. Making up...
Not only was their foundry 10nm absolutely non-functional in hilarious ways, they also burned down bridges on 14nm, denying their broken process was at fault for issues for over half a year to customers.
Such workloads are covered in the suit, see Perlbench for PHP-like stuff and there's compression as well.
The point of SPEC is that it casts a wide enough net of workload types with different characteristics that it should be an aggregate representation of performance.
We don't have a good...
Prefetchers are a lot more lax than mobile A76's, so it's not even being as aggressive as it can be. The thing is just cache and bandwidth starved at high core counts, it should have had at least 64MB, 128MB even better, this is one aspect where I expect Rome to beat it quite easily, and I'm...
Apple being ahead in ISA is actually a weird contractual anomaly, without Apple, those ISA revisions wouldn't exist. I wouldn't put much worth and weight into the whole thing.
You should expect a whole new lineup of several cores from Arm in 2021 on v9.
I don't understand what you're even trying to convey here, I was bringing up how system wide IPC is a stupid metric since you were normalising "clock" for a system wide metric, at the same time I can normalise processors as being a system wide metric at which point it doesn't matter how many...
Even if you live in the land of the obtuse and count aggregate instruction throughput across all cores in a system I hope you're also counting more clocks since all the cores together tick more together right?
I find MT IPC discussions stupid as at that point you're not discussing about a...
I can't comment on the Ampere, but you'll have equal-compiler figures from us on Graviton2/Cascade/EPYC.
They're stronger IPC than Intel/AMD, but not by a lot.
There's some SIMD in SPEC, but it's not like it's a math crunching HPC test that fully utilises it. For the workloads that it's meant...
The biggest hurdle for Windows on Arm Mac is graphics and the GPU choice Apple will go with. We might have some surprises here - I don't know which way they'll go, I have doubts they'll write Windows drivers for their own GPU.
It is FP32, the smaller mobile variants reach 1TFLOP: https://images.anandtech.com/doci/15178/Snippet.png
I don't remember seeing that RockChip roadmap, but Natt was a rumoured codename for G77, and that chip should very much be G77.
HiSilicon will be jumping to A78.
IP is not tied to any...
Scalar IPC is the hardest design characteristic to achieve, the A64FX doesn't look that great other than it being an SIMD and bandwidth monster.
In regards to Apple's freq scaling, people forget Apple still has to cater to energy efficiency. Simply using fatter transistors, going above 3GHz to...
That presentation is from 2015, you mean to say they didn't implement those features yet? I'm not familiar with the track-record on the matter, I'll have to look into it.
There's not *that* big scaling difference between the two, 2017 is more memory heavy - for example you see AMD doing better on Zen2 on 2017 in relation to Intel than on 2006, and my take on it is because AMD has a stronger core memory system than Intel right now (Yes Im talking at the core...
As equal to what? Who's to decide "how benchmarks are done"?
The rate benchmarks in their characterisation are almost identical to the speed versions, with runtime being by far the biggest difference, and that imagick is missing from the rate suite.
When I went ahead to decide on all of this...
I don't know who you asked on Twitter, certainly not me.
The 9900K SPEC data out there was on 3200CL16 as described in the article.
Yes, this is admittedly wrong and it should have been 2666 from a product standpoint - it was run on an available system at the time and I had forgotten to...
I have no doubt SoftBank is one of the reasons for Matterhorn. SoftBank invested an idiotic amount of money to buy Arm and their end goal is to actually have the company go public again in a few years and recoup their investment. The main growth opportunity here is the infrastructure and HPC...
Your argument is flawed.
First of all, the A77 is only marginally larger than the A76. PPA on the A77 is better than on the A76.
Secondly, what makes you think that Matterhorn will be the single "big" CPU offering alongside their small cores instead of it simply being the new "giant" CPU...
There was no direct coverage of the keynotes allowed. In general nothing concrete other than "we're working on bigger stuff and make everything better" and that Matterhorn will have 256-bit SIMD. It was just a teaser, expect more info next year.
https://www.anandtech.com/show/13226/arm-unveils-client-cpu-performance-roadmap
Hercules is going to be the smallest update perf wise from the Austin family, ~10-15% upgrade with process.
What Sophia made in the past doesn't constrict them on what they work on. Yes Matterhorn is a high-perf/HPC...
Hercules is a smaller update. Matterhorn is a v9 high perf core with 256-bit SVE that finally gives up priority on small die area, and will be a super wide µarch. I would expect it to catch up with the A12/A13 - the issue is that yes that would indeed mean a 3 year gap between products, but...
Keep in mind that we won't see post-Williams developments for another 2 years, and then they hired Mike Fillipo from Arm so I guess they're in a good state to continue their trajectory.
Energy isn't power... those Arm figures are CPU only figures yet there's also memory and other things that add to it.
I tested the little cores earlier in the year: https://images.anandtech.com/doci/14072/SPEC2006eff-overview.png
The A13 Thunder cores in that graph are
int2006: 380mW, 3167...
Memory latency testing is hard, all the popular tools out there are just wrong. Core-to-core roundtrip is basically 2x L3 latency, which makes sense as that's essentially how it works.
For the sake of clearing facts; the voltages are from the chip's voltage tables, I won't comment more on that. There's also GPU and the small cores.
Also this is the first time I hear f/v curves being common across process and not taking uarch into account. How the heck do you account for...
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