Your calculation is wrong, the 1.23 clock speed gain is the 20% performance increase that Samsung's 14 nm process gives, your double counting it in your calculation.
There is a post on the RWT forums about an update to the Intel Optimization Manual that includes new details about Skylake.
http://www.realworldtech.com/forum/?threadid=154100&curpostid=154100
One of the most interesting is the fact that Skylake has 5 decoders, up from 4 that Intel has had...
At this point all we have is Apple's claim of 1.8x A8X for A9X and Intel's claim of 2x A8X for the m7-6Y75. We will have to wait until real benchmarks (something better than Geekbench) are run to see how it turns out.
Where are you getting 40%? I see a C2750 does 1898 in single thread Cinebench R10 at 2.6 Ghz (its turbo) while a 2.6 Ghz E4700 does 2943, that's 55% more.
Yes it is, its still far far better than a toy benchmark like Geekbench 3. Spec2006 would be a lot better, but even that is outdated, a new Spec suite is long overdue. As for broken subtests, that is why I gave 176.gcc, that subtest has not been broken.
I wouldn't be so sure its going to be the fastest tablet SOC, that's from Geekbench 3 a practically useless benchmark. Geekbench 3 shows the A8 with around Haswell level IPC while the far better SPEC2000 benchmarks shows roughly Core 2 level IPC.
Anandtech did a SPEC2000 run in its iPhone 6...
That is the current HEDT and server socket, the new sever socket is supposed to be Socket P. Where did you see it said that Skylake HEDT is no longer going to use the server CPU's and socket?
They have to change the layout anyway because of AVX-512, is not in the client silicon at all. The impression I got from Kanter was that the power saving from going 4 way was trivial, that the real savings was halving a 512 KB L2 to squeeze the client silicon into a 4.5 watt TDP. Apparently the...
They said on the podcast that the 4.5 watt TDP version was a late requirement for Skylake and resulted in significant changes to the design. So the lack of AVX-512 and possible halving of the L2 from the Xeon version may be a result of them squeezing client Skylake into that 4.5 watt TDP.
There was an interesting podcast about Skylake with David Kanter over at Tech Report. One of the things talked about was the L2 cache, its associativity was lowered from 8 to 4 in Skylake. Kanter thought that was probably because they increased Skylake Xeon's L2 from 256 KB 8 way to 512 KB 8 way...
It's not wrong just using different benchmarks, for example Tom's Hardware 2015 CPU charts gives for Total Time:
I7-975 EE (3.33/3.6) 1854
I7-2600K (3.4/3.8) 1678 10.6%, about 8.2% clock adjusted
I7-2700K (3.5/3.9) 1638
I7-3770K (3.5/3.9) 1523 7.6%
I7-4770K (3.5/3.9) 1385 10%
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