I know that it's more than two years now, but I will be grateful if you can add more information about the test configurations.
Test configuration for the Ryzen 1800X platform
Motherboard: Crosshair VI Hero
o.s.: Windows 10
Memory: 2666Mhz, but which model(s)?
HD/SSD: which one?
What are the...
Exactly. And of course, if there's some huge advantage, even big companies, with a consolidated partnership with Intel, can change. Never stated the contrary.
Right, a vendor can ask for some instructions, and AMD can provide them. But this requires time.
A cannot disclose information about similar scenarios, for obvious reasons, but this process (going from the customer request to the final availability) might require yearS. And I'm not joking...
I never stated the contrary. I've just reported the current situation, and that it's not that simple to switch CPU vendor.
BTW, Intel bought Altera, and has started shipping Xeons with integrated FPGAs...
No, they handled themselves merging the selected patches that they want to be applied to their customized software.
It's a pain in the ass, but such big companies have resources to do it.
Well, it's very well known that at least Google has a proper, own Linux fork, which is internally maintained. Microsoft... is A BIT closed source. :D
The same thing can happen with other big vendors which have proper, internal infrastructures, which run their customized software.
The software...
The reported part was NOT talking about AES acceleration, which is common and a standard part of x86's ISA. Same think for video compression.
The specific part was talking about OTHER, HIDDEN, chip features which are enabled ONLY for SPECIFIC customers.
So, here is it that hot part:
Another way to make a chip faster is to add special circuits that only do one thing, but do it extremely quickly. Roughly 25 percent of the E5’s circuits are specialized for, among other tasks, compressing video and encrypting data. There are other special circuits...
Absolutely with ...
So... I beg to disagree. :)
Then I better specified what's the states of the server market for big companies which make use of Intel's Xeons. ;)
Absolutely... no. It's known that Intel has developed custom extensions to its CPUs for specific (BIG) partners, which are enabled only for such partners.
So, it's not as easy as it can be to switch to another CPU vendor.
That's why I'm warmly waiting for some test with emulators, compilers, etc. ;)
At least Intel's one is out. :p
As I said many times, it's better to wait for a wider set of tests.
However I think that AMD chose Blender because it favored its micro-architecture. So, it's like an upper/best...
Well, the scene used by AMD for the Blender test doesn't seem to be so complicated to stress a lot the L/S unit. On the contrary: it's quite simple.
But unfortunately AMD haven't released the data file, so that some runs can be made with a profiler to extract such data.
Well, the processors...
Yes, and the situation hasn't changed: we don't know how many stages XV has. We don't know the FO4 of Zen. We don't know the fMax.
Therefore, we cannot make any assumption, since the microarchitectures are, also, quite different.
And there's no data about Zen's FO4 and fMax. As well as there's no clear information about XV's number of stages.
So, no comparison can be made for such variables, and no conclusion can be made, as well.
Time to try Python:
http://python-development.blogspot.com/2016/03/why-do-many-data-scientists-love-using.html
https://www.quora.com/Why-is-Python-a-language-of-choice-for-data-scientists?share=1
http://bellm.org/blog/2011/05/27/why-astronomers-should-program-in-python/...
Exactly. Emulators usually are strictly single-threaded applications.
When/IF they use more core/threads is because the main thread (the one which emulates the CPU) offloads some o.s.-interface tasks to another thread (usually the "GUI" one), like displaying the elaborated framebuffer, updating...
I see. But at the beginning of the document there's a list of lawsuits between AMD and Intel, and it isn't reported the specific one regarding the compiler "issue".
It WAS, not it is. And from long time, if you take a look at end dates of the listed episodes.
Intel changed A LOT.
There's also one free "int" port, which can also handle branches. ;)
But the rest is, and it's also important.
For example, once you have parsed a large blob of text using the re or csv module, you want to manipulate the result, and for this Python code / CPython's VM is used... which isn't...
I haven't said anything regarding this. It might be true.
No, that's what for the unfair competition in the 2002-2007 period, for abuse of dominant position.
No. As I reported before, the code path selection follows an (Intel's) micro-architecture criterion. Otherwise a fallback/general...
That's not true. Intel compiler optimized code for SOME of its micro-architectures. It means that the optimization didn't worked even some Intel processors.
The reason is "simple": such optimizations work on a micro-architecture basis, instead of features basis.
Which is obvious if you take a...
Which does't use AVX/-2... :rolleyes:
It depends on the emulated code/instructions, but I think that it's reasonable to expect an IPC close to 1.
It doesn't change the picture: they are not enough. Not even the L1C is enough. And we don't know the politics which are used to cache the uops...
Yes, but the micro-op cache is very small, at least compared to the regular L1C. And we don't know how it works. For example, it might work well only for loops, and have scarse or no associativity at all (e.g.: only a few "fragments" are cached).
Long story short: with "fragmented/heavy-branch"...
IPC is a mean, and that's what I expect to be used when more applications are involved to calculate some "aggregated" IPC.
Well, even emulators have loops, and a bigger loop (the main, "evaluation", loop at least), but it doesn't mean that a uop cache can be of any benefit.
If you take a look...
3 256-bit VecInt ports should enough. ;)
It's AMD that stated the +40% IPC over XV, not me. Don't you trust what AMD reported? :p
Guess what: you run/test specific applications to get some IPC number.
Well, nobody stops to take other metrics to measure something else.
If the IPC definition...
I don't subscribe it, as we already discussed here around 1 month ago.
And according to the Blender results, Broadwell(-E) resources guaranty almost exactly the same result. ;)
Sure, but Intel's scheduler has a better chance to feed its ports, since it has an exact "vision" of the platform...
You have to see how many uops can be dispatched per clock cycle by the micro-op cache: this is the bottleneck.
Intel processors can dispatch 8 of them, and the scheduler works in the best condition (it has the complete "vision" and can make the best decision).
Last but not really least, the...
But they are very very limited, as you can see: 256-bit instructions are rare birds.
The biggest part with Blender is represented by scalar code, or at most some 128-bit vector usage.
I doubt that the whole speed-up of this patch is related to the 256-bit vector usage. Unfortunately there's no...
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