Nvidia is a company with a ‘hammer’. Nvidia’s mobile offerings had great promise but too much of the power budget was allocated to the GPU. Great for handheld games but not mobile phones. Power matters and you have to use what the technology of the day gives you. ‘Heavy AI’ is apparently...
This is about die volume and extending capabilities at the lowest cost. The Max die is already fairly low volume. An ‘ultra die’ would not pay for the mask set. Extending Max into multi die packages can increase the die volume for the Max with a little packaging cost.
AMD covers from 8 to...
Nvidia has the cash flow to reserve capacity but the question will be yield. If they redesign for multi-die products they might be able to adopt a node earlier. However if they still want 700-800 mm2 die then they will probably still trail.
Not really. I think it is a good educated guess but I am not big on rumors. Apple has the need and a cost advantage so it makes sense that Apple would roll their own. Will it be by 2025, who knows? Educated guessing.
The margins for X86 CPUs and GPUs are fairly clear with both AMD and Nvidia using wafers from TSMC and reporting on gross margins. Intel’s transistor costs have just be broken out into a foundry line item to clarify their costs. Apple is buying enough wafers to get preferred status either at...
Back when Intel was late on 14 nm and they showed notional yield curves they had a footnote that the yield curves were aligned with HVM and the definition was 1 million die in a quarter. That is not many wafers. When I did the math that was less than a FOUP per day. Intel started with U and Y...
Apple is raking in ‘astronomical’ profits on the high volume but there gross margin actually dipped a bit in the last quarter from last year, from 43% to 42%. You know who else has good margins in computing, Microsoft, Intel and AMD. Microsoft gross margins on Windows has been close to 90%...
Not really. The main problem with Apple at the time of Jobs return was shrinking volume which is a death knell in computing. The candy colored iMacs, the agreement with Microsoft to continue developing software and the eventual shift to Intel processors is what saved the Mac business. Apple...
What is the source for this data, all I have seen officially from TSMC in there annual reports is there 10%+ customers, in other words Apple.
The Qualcomm data is not really that surprising. Qualcomm was the largest and only 10%+ customer of TSMCs when Apple was still at Samsung and they...
My speculation is that M processors will transition to MacBook Airs and iPads with the M Pro eventually being the lowest processor for the MacBook Pros when the ‘dust’ settles. The M in MacBook Pros for this generation may be an indicator of wafer limitations. The MacBook Air, iPad Pro and...
This isn’t engineers this is skilled craftsman. Here is a quote from ASML on installation of EUV.
Peter Wennink
Good question. We need to realize it. If you look at the reasons, predominantly the push-out had to do with fab readiness and that was basically driven by construction skills. And...
I think the chips aren’t delivered until INFO POP packaging is complete. Details of the contract and partial payment aren’t public. How much yield risk is their in packaging and has Apple accepted all that risk from TSMC?
I am not claiming any expertise here but I have always thought that Apple probably purchased DRAM PHY IP from either Synopsis or Cadence. As an extremely large purchaser they probably have some influence over the design but they aren’t doing it alone. Cadence has TSMC 5 nm PHY available...
With limited supply of EUV machines and the number of EUV machines and the differing requirements for N5, N3 and N3E there is going to be some bias from TSMC to keep people or push people onto processes that use fewer machines. The number of wafers and customers they can satisfy increases...
The Apple A4 was built on the 45 nm node at Samsung, at what I believe was Samsung’s Austin, Tx facility. Apple stuck with Samsung in Austin until their wafer demand was equal or starting to exceed the 40K wpm capacity of the Austin facility on the 28 nm node. (still larger than the 22 nm that...
The probability that a node from Intel is less than a node from TSMC is very unlikely. It could happen but it would really take TSMC screwing up almost as dramatically as Intel. TSMC has a lead customer in Apple that is very unlikely to ever switch to Intel. Even if Otellini had offered to...
I believe that TSMC is doing all of the packaging for Apple on both A and M processors which means that revenue recognition probably follows packaging. It seems like there is an inventory build at TSMC prior to revenue from Apple in fall.
I am pretty certain they do have a ‘founders‘ IP agreement. How much it is worth and what ‘rights’ it gives them in licensing is a separate issue.
Arm was founded with 1.5 million pounds in cash from Apple, 250 thousand pounds in cash from VLSI and ARM brought only the IP valued at 1.5 million...
A engineering blunder isn't too hard to imagine but it could be combination of factors. The iPhone 14 PRO has a new processor with a larger die on N5, which is more expensive to manufacture than last years processor. One scenario is that when it was being designed the plan was to use N3, which...
Here is a link the overall bill. The CHIPs Act is still only 52 billion and the rest is supporting a lot of the science programs, e.g. NSF. NIST and NASA.
https://www.commerce.senate.gov/2022/7/view-the-chips-legislation
Here is an excerpt from the CHIPs part of the bill.
"$39 billion in...
The fact that they are converting a research fab to a 'production' fab suggests to me that TSMC purchased additional equipment to handle Intel's contract/demand. The Intel demand was added to the production schedule too late to build a 'production fab' specifically for Intel but the demand...
Node names don't have a correlation with transistor densities but transistors do have some physical dimensions in the 'patently ludicrous' dimension with fin widths being around 7nm since the 14nm FinFET. The fin width on N3 is probably still around 6 nm for physical strength. The fin and GAA...
What is meant by revenue? The revenue for Apple is based on wafer and packaging purchases by Apple from TSMC at about 25% of the $60 billion in TSMC revenue. Apple buys a lot more in both wafers and packaging than AMD or Qualcomm. If you give Apple an internal transfer margin of 45-50%...
This doesn't say much about the specific number of EUV at either TSMC or Intel but it does discuss the upcoming shortage of machines to fill all of the clean room space.
"I believe there will be demand for 20 more EUV tools than ASML can produce each of the next 3 years. To put that is...
Without direct knowledge I can tell you with assurance that they have thought of backup UPS. These are competent engineers and business people. I will speculate that they have UPS on control systems but it is too expensive to back up the whole manufacturing process. Risk management is both...
GPU's are typically wide and slow to keep them power efficient.
My understanding is that the ASML 5000 machines being shipped are development machines to 'get familiar'. The ASML 5200 that Intel ordered is supposed to be the first production machine. I don't know where Intel is on process...
It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;
"Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build and deploy...
witeken posts as Arne Verheyde on Seeking Alpha and his last post from Feb 10 says that he is still long on Intel but he is neutral on Intel and looking for answers in tomorrows Intel Investor days.
I will speculate that the five 5000 NA EUV research machines will go to Intel, TSMC, Samsung...
I think EUV was so late that double patterning hasn't really gone away. Here is quote from a Scotten Jones article;
"TSMC’s 5nm process currently in production has a 28nm M0 pitch and we believe this one layer may be double patterned EUV in current production while the rest of the layers that...
It is a fairly large bucket with all of the physical, QCT broken out from the licensing QTL.
For the last three years the margin in QCT for EBT has been;
2019 - 14.6% on 14.6 billion in revenue
2020 - 16.8%
2021 - 28.7% on 27 billion revenue
The revenues increased significantly in 2021 and...
I have been under the impression that ARM is in the room with TSMC while the node is being developed. TSMC often uses an ARM core to assess improvements in power and performance. ARM typically has a new core designed for the new node and ARM licenses Physical IP very early in the life cycle of...
I think the answer the question on why Qualcomm is working with Intel is in this announcement from the Government on a contract for RAMP-C.
"This opportunity has been awarded to Qualcomm Technologies and Intel Technologies."
The Department of Defense (DoD) currently has no on-shore access to...
To tack on to this I think when you looking at die volume then Apple's is definitely cost advantaged.
The x86 eco-system sell around 60 million laptops per quarter and 20 million desktops per quarter or about 80 million and 240 million per year...
This isn't definitive but one of the first slides from the presentation was
'M1 has its own storage controller, and Apple is using the latest flash technology'
The processor 'map' with the 'features' shows and NVMe controller incorporated in the M1 die. Apple purchased Annobit and started...
High volume manufacturing is a very loose term, at least according to Intel. When they were ramping the 14nm node they had a footnote on the bottom of a slide that their definition of high volume manufacturing was 1 million die in a quarter. The die that they were using to say that 14nm was in...
Lots of guesses and speculation on my part. I don't know anything.
In these discussions on wafer capacity the wafer size always needs to be specified. Intel has around 800K+ wpm of 200mm equivalent wafers per the latest report from IC Insights. TSMC is running about 2500 wpm in an...
This is a fine point but the POP packaging on the A12 is a process developed by TSMC called InFO with TIV (through insulator via) to reduce the wire lengths and improve thermals. I was really disappointed when Anandtech did not do a full blown analysis when Apple first utilized InFO packaging...
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