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  1. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Even AMD's GPUs are essentially DoA for training. Nvidia has massive software, interconnect / scale advantage. The new compute unit for them are racks with massive interconencts between the gpu. Google is the only one (as far as I know) that has similar interconnect infrastructure. AMD and Intel...
  2. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Lion Cove's branch prediction is very disappointing. Already previous P cores were rather medicore compared to Zen. Now looks like P core is even falling behind the E core.
  3. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    14A is supposedly still in development. Don't be surprised, if gains change. They only got their first high NA a couple of months ago.
  4. J

    Question CPUs for shared memory parallel computing

    Mathematica is supposedly using Intel MKL, which does support avx512. The question is just if Intel enabled AVX2, AVX512 support on AMD cpus. I've been using Mathematica in my student years and I can't say good things performance wise, except if you are really using only highly optimized...
  5. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Let's first clarify what FAD is. My understanding is that FAD is technology that is created without a meaningful intent to solve a particluar problem. Intel has some FADs: neuromorphic computing, quantum computing, silicon photonics research group. Maybe I missed something, but I thought Intel...
  6. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    It's not just insane, there are some claims in there that just don't make sense - big red flags. Like merging P and E cores. P and E are made for a completely diferent power envelope. Merging them would create what? A core that is best in both envelopes at the same time? "Aleee" teams? Could...
  7. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    What does 24 wide issue even mean? 24 wide decode?, 24 wide execution?, 24 muOps from muOp cache to execution? Dividing larger core to multple smaller cores is quite insane idea. How would that work, what would be the latency to switch? How would private caches divide and what would happen to...
  8. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Pantherlake is supposed to launch in 2025 on 18A...
  9. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Skymont design definitely seems very modern and sophisticated, but the question is: "can it achieve same IPC, vector throughput, frequency... as P-CORE without having P-core size (and power)?". It seems that Intel's P-core dedicate a lot of die space to lower latency instructions and vector...
  10. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Does anyone else thinks that 15% IPC gain of Lion Cove is quite poor given all the changes in the core? They beefed up every part of the core, separated int and float, scalar int mul throughput is up 3x, new cache structure,.. Sounds almost like Intel is sandbagging and the gains in some...
  11. J

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Didn't really follow all the debate here; any info on AVX512 implementation? Can it do 2x AVX512 / cycle? Doubled load bandwidth seems to indicate it can load 2x512 bit, which is on par with Golden Cove.
  12. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Imo, there's no way Skymont has better fp than GLC. Maybe for scalar and 128 bit vector. GLC has 2x256 bit fma, new adders, 3X256bit load / cycle. Maybe it'll be close in everyday apps with limited amount of vector code. See chipsandcheese golden cove analysis; Golden cove core has huge...
  13. J

    News Intel 1Q24 Earnings Report

    Any word on SRF production? Shouldn't 20A also be in volume production now? They were targeting q2 launch.
  14. J

    Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

    Intel to use direct self assembly + high-NA euv for 14A process: https://www.semianalysis.com/p/intels-14a-magic-bullet-directed Apparently this is why Intel is buying all these high NA tools. According to the link, Intel could scale M0 metal pitch all the way to ~20nm, which seems again very...
  15. J

    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    I wonder what's preventing Intel from expanding their capacity. Is there some other bottleneck besides EUV tools? They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool. This seems very irrational decision. Wouldn't it make much more sense to ramp 18A as fast as...
  16. J

    Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

    How many production capable EUV machines does Intel even have now? A year or two ago there was a lot of talk about Intel lacking EUV equipment and now they want to manufacture their own stuff + chips for customers. 18A process is supposed to use EUV on multiple layers, which just makes the...
  17. J

    Discussion Intel current and future Lakes & Rapids thread

    Just FYI guys, Ice Lake and Tiger Lake seem to be able to execute 2 instructions per cycle for a limited subset of avx512 instructions (this is on zmm registers). Check out: https://github.com/InstLatx64 This is still a very minor improvement in throughput, because Skylake already did 3x256 per...
  18. J

    Discussion Intel current and future Lakes & Rapids thread

    The fact is that some avx512 instructions using zmm registers show throughput of 0.5. How is this possible if the thing does not have two avx 512 units? It does not have full 2 x avx512, but it does more than 1 x avx512 per cycle.
  19. J

    Discussion Intel current and future Lakes & Rapids thread

    I'm more reading than writing, but this is interesting. He didn't confuse anything, but he did look at the wrong lines. 512bit fma should use zmm registers. These lines show expected numbers; 4c latency and 1 for throughput. There are avx512 instructions that operate on lower width vectors and...
  20. J

    Discussion Intel current and future Lakes & Rapids thread

    Isn't this the goal of such a chip? To get the most performance from the given tdp? Laptops are not meant to be run at 100% load for long periods anyway, unless you like running your laptop at 90 degrees. The purpose of the small cores is to increase MT performance and keep reasonable tdp.
  21. J

    Discussion Intel current and future Lakes & Rapids thread

    I thought we are getting 8 core TGL in Q1 2021. At least there are rumors about it.
  22. J

    Discussion [SA] Intel should not launch Ice Lake-SP

    There is Granite Rapids tag at the bottom of the article, so that may be the product Intel is out-sourcing. There are also GAA, 3nm and 5nm tags. So the article is probably also talking about Intel going gaa at 5nm since, if I remember correctly, TSMC announced that they are staying with finfet...
  23. J

    Discussion Intel current and future Lakes & Rapids thread

    Desktop / notebook Tigerlake will have 256kb L2 and 3mb L3 / core. There were some leaks; maybe wccftech has news about it somewhere and there were also some twitter posts. My impression is that large L2 caches burn quite some power - see Bulldozer, Skylake x. Besides, when comparing client...
  24. J

    News [Toms] Intel Announces Socketed 56-Core Cooper Lake Processors

    It is really beyond me, why doesn't Intel take the same approach as Amd. They are clearly capable of making <100mm^2 dies on 10nm, so an 8 core Icelake chiplet shouldn't be a problem to produce. The era of large dies seems to be getting to an end, because process complexity and defect rate per...
  25. J

    Discussion Intel current and future Lakes & Rapids thread

    Yes of course, Icelake and Cannonlake have a new integer divider with much smaller latency (18 cycles down from 97 in Skylake). Avx2 also lacks many integer simd instructions which avx-512 does have. This totally explains it. It also means Icelake is going to be awesome for scientific...
  26. J

    Discussion Intel current and future Lakes & Rapids thread

    What's going on with 3DPM avx-512/avx2 ? 4 times as fast as Whiskey Lake, but theoretical flops are the same. Icelake does have one more shuffle and much improved load/store but it does not explain such differences.
  27. J

    Discussion Intel current and future Lakes & Rapids thread

    This is very strange. Intel's transistor counts may be a bit off. 8 core Coffee Lake measures ~175 mm^2 and it also includes gpu. Ryzen at 192 mm^2 has no gpu. Coffee Lake has generally higher ipc, clocks better and also has native avx2. So either amd produced subpar design, requiring a lot more...
  28. J

    CPU for Floats crunching

    Check out ebay for xeons v4 (2696, 2697, 2698, 2699 v4). Some are quite cheap. Strong cores, lots of cache, high bandwidth, reasonable price ->hard to beat. you can get 18-22 core cpu for good 500$, sometimes even cheaper. If you are fine with OpenCl, you can also try R9 280/290x or get a used...
  29. J

    New Zen microarchitecture details

    Maybe some ESs came from GF, wheareas others were from Samsung. https://twitter.com/BitsAndChipsEng/status/814894218544037892
  30. J

    ZEN ES Benchmark from french hardware Magazine

    So it's B0 or similar.
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