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Since Ryzen's L3 stores shadow tags to data in the L2 caches of the cores within a CCX, it might be argued that it sort of behaves a little bit like an inclusive cache. (If there's an L3 miss it checks the shadow tags to see if the data might be in another core's L2 cache before (accessing...

The problem was essentially what I described here: (except it's technically not really 'false sharing' in this case, though the effects are identical) http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/ryzen-strictly-technical.2500572/page-23#post-38790480 I initially thought it might have been bandwidth...

Hi everyone, Just to update on a post I made earlier this year: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/ryzen-strictly-technical.2500572/page-9#post-38776310 I took a crack at solving this issue and the problem was indeed due to false sharing. CS: Go uses a very similar lightmap baker to the SDK...

I don't think it really suggested that it was an issue with the Intel compiler, just that the Intel compiler does some things differently. The purpose of linking the stack overflow question was that it gives a bit of an explanation of how it works (writing directly to ram), as well as that there...

More just a run-down of what it does rather than any related performance issues. As I gather the performance issues with this is fairly unique to Ryzen. [removed]

Seems like they were using _mm_stream intrinsics which write directly to RAM. EDIT: I'm not going to pretend that I really know what's going on with regards to this, I've never heard of this issue before, but my theory that false dependencies cause inordinate problems for Ryzen might not have...

https://twitter.com/FioraAeterna/status/847472586581712897 https://twitter.com/FioraAeterna/status/847472836344033280 Changes that improved performance in Ashes were not related to thread scheduling, but rather fixing false dependencies caused by the use of an SSE instruction, apparently.

It's very easy to test the wrong thing with a micro benchmark, should be very careful about such things.

Here's something that might be interesting. It's about the history of the scheduler in Linux: https://blog.acolyer.org/2016/04/26/the-linux-scheduler-a-decade-of-wasted-cores/

http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/ryzen-strictly-technical.2500572/page-11#post-38776963 There is a fairly severe latency bottleneck when accessing L2 caches on the opposite quad core module on the PS4. On the PS4 die there is a fairly large physical gap between the quad core modules. Or do...

Given that they apparently didn't give enough lead time to motherboard OEMs (which i'd consider to be far more critical), I don't see this as particularly shocking.

I don't think this thread is an appropriate place for this.

You would think that the most basic information about a product would be conveyed correctly, or that someone aware of it might speak up when false information is on the product packaging and spec sheets themselves.

Is it? That's interesting. I wasn't aware of that.

I should note that a real-world case of false sharing would not necessarily have to show 100% utilization on any thread due to the polling interval. The tests that produces the utilization graphs in my post were designed (by the author, not me) to only test the effects of false sharing...

Unfortunately my attempts at writing a micro benchmark have produced wildly inconsistent results, so I do not feel comfortable posting them until I figure out what's going on, of which I don't have any more time for today. (It can be very difficult to test the right thing with micro benchmarks)...

Allyn Malventano from PCPer: "The C++ apps are incredibly simple and are only creating threads or pinging between cores. If such a simple app must be rewritten with workarounds just for AMD processors, we have a serious problem." Unfortunately they're completely missing scenarios where...

If anyone wants to know what dual e5-2680's (8 core / 16 thread SandyBridge-EP chips) look like in Core Info (v3.31) on Windows 10 64-bit, in comparison to an R7-1800x, here you go: EDIT: Put it in code tags since it uses a mono-space font. Dual e5-2680's: (total 16 cores, 32 threads combined)...

For anyone interested in the similarities to the PS4's core organization (2 quad core modules, like Ryzen): http://www.dualshockers.com/2014/03/11/naughty-dog-explains-ps4s-cpu-memory-and-more-in-detail-and-how-they-can-make-them-run-really-fast/

The idle power characteristics of Ryzen appear to be fantastic. I could imagine a Ryzen APU being a great part in a laptop.

I've spent some time working with two people ('Longcat' and 'iWalkingCorpse' from AMD discord) with Ryzen systems to test Valve's CS: Go map compiling tools on Ryzen. I believe the results support the notion that the inter-CCX fabric can cause potentially significant slow-downs when the...