Mostly correct, at least from what we know. When there's a data request for data that isn't on the local CCX L3, a strobe is sent out to the second CCX's L3 caches and to RAM at the same time. There's no information about the local CCX request being done at the same time, although it would make...
Look at the labels for the graphs again. "cTDP" is a configurable thermal envelope that can be adjusted in the BIOS, which is how Stilt managed to get these results more accurately than other sites just making voltage or frequency adjustments. The most I've seen others do is manage clock speeds...
When a request or a ping is made to L3 in a different CCX, both L3 cache in that second CCX and the unified IMC are pinged/strobed/checked at the same time.
If the inter-CCX latency of 140ns average is correct, then it can only be that the two latency values are being reported together...
Actually, the scheduler is working as intended, it's the core parking settings that are not. This is why AMD is issuing an update in the future to add tweaks to the balanced profile to improve performance, and they're going to alter the core parking settings.
To clarify all the CCX stuff, I've sent a few questions to my contact at AMD and hopefully we'll have some answers by the weekend. I specifically asked about latency to all points of the system, including from CCX0 to IMC1 and IMC2 in a Ryzen 7 processor.
I'm not too clued up on how Ryzen's...
For those of you still testing inter-CCX communication and trying to set core affinities, Ryzen has a peculiar habit of pinging/strobing both RAM and the L3 cache in adjacent cores when the L3 cache of one core doesn't contain the needed data. If it doesn't receive a reply from either of those...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.