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  1. M

    Ryzen: Strictly technical

    Ok, I bow to your guys superior knowledge of how console processors are built :)
  2. M

    Ryzen: Strictly technical

    They are, 4 2-core complexes (grouped by 2) all connected by L2 cache - long comparison to CCX connected by Infinity Fabric even if "communication between them is not ideal". But ok, you have a point there that it resembles CCX in Ryzen :)
  3. M

    Ryzen: Strictly technical

    No, consoles do not have CCX, they are based on Jaguar core, if anything they have 2-core complexes, four of them. You are right, you were testing worst case scenario :) Now I have to see that for myself on my PC :) so just have to find some time to do the tests.
  4. M

    Ryzen: Strictly technical

    What does console design have to do with it? Console CPUs do not have CCXs. I was talking about forcing games to run on 4 cores belonging to one CCX or 2+2 from different CCXs in Windows by pinning them to cores - you can test any configuration that way - it's just that you can't simulate real 4...
  5. M

    Ryzen: Strictly technical

    So it seems. I will test it myself in various games in 2+2 and 4+0 config then in Windows with forced cores association with 8 cores active.
  6. M

    Ryzen: Strictly technical

    So it seems my error was in not completely powering down my PC between changes. How stupid of me...
  7. M

    Ryzen: Strictly technical

    I have no idea what you are implying - 4+0 (8MB of L3) as in Ryzen 1200/1300X/1400 is in fact 2+2, it is not 4+0. They are Ryzen cores that have errors in "lower" or "upper" halve of L3 cache (look at CCX schematics how that works). And yes, differences in games are there but due to cache size...
  8. M

    Ryzen: Strictly technical

    Nope, even on R7 you can't get 4+0 config. I know, I have tried on few boards. You only get 2+2 even if you select 4+0. Ping core to core shows that it is not working. Yes, I can use more then 4 threads, but not cores. Windows prefers cores to threads and it won't put a 5th thread on SMT core...
  9. M

    Ryzen: Strictly technical

    There is no way to test such because bios setting between 2+2 and 4+0 are ignored. You could conceivably test it by forcing program to use specific cores but that would require R7 CPU to even try and the results would be tainted. You can't test 2+2 / 4+0 on 1500X anyway - bad example.
  10. M

    Ryzen: Strictly technical

    And increased L2 cache sizes - in all, small decrease. You ask, why would I be left with cross-CCX traffic - because some programs (games) use more cores and while Windows is aware of CCX topology, when the game requests 6 threads and they can't be on 4 cores because of load balancing, it...
  11. M

    Ryzen: Strictly technical

    1. Cores inside CCX are not connected to each other, they are only connected to L3 cache - so only 2 additional links to L3 cache would be needed. https://www.custompcreview.com/wp-content/uploads/2017/06/amd-ccx-epyc-cpu-presentation-slides-1.jpg - there you can see 6 links inside L3 cache and...
  12. M

    Ryzen: Strictly technical

    Unless the CCX would grow to 6 cores, as I suppose it is "destined to" grow in 7nm ;) While 3 CCX complexes would complicate things, two bigger ones would largely not affect the overall design - after all CCXs are connected to IF by L3 cache and you would simply add cores and connect them to L3...
  13. M

    Ryzen: Strictly technical

    Well, they might have been able to do it like this: i.redditmedia.com/--EzP2t4YMf9TCYeibbG29tu3Ajfeje5QjrvCk8g1uI.png?w=572&s=d4d21987be37de7cfc9679f1aff4d5ea - but I do not know if RyzenMaster would correctly show it as 4500Mhz.
  14. M

    Ryzen: Strictly technical

    I was just curious about your opinion, if their results came from specific configuration of 2700X CPU and if so why did 1800X also cross power limit - if it was a standard case for those Ryzen CPUs. I have found an interesting review -...
  15. M

    Ryzen: Strictly technical

    According to above numbers, 1700X or 1800X also did not respect power limits - is that what you have noticed in your tests too?
  16. M

    Ryzen: Strictly technical

    Thank you :) back to Bios for me :)
  17. M

    Ryzen: Strictly technical

    Thank you for your explanation :) Are the tools you are using to set power limits "propriety" or can you share them? It would be very useful to be able to lock power use without constant rebooting.
  18. M

    Ryzen: Strictly technical

    This is how TomsHardware is measuring their power use: https://www.tomshardware.com/reviews/power-consumption-measurement-cpu-gpu-components-powenetics,5481-3.html This is measured between power supply and 12V connectors on the motherboard, so if they show low power use... on the other hand, the...
  19. M

    Ryzen: Strictly technical

    http://www.guru3d.com/articles_pages/amd_ryzen_7_2700x_review,4.html has a helpful table that explains which CPU+chipset combo has what USB connection.
  20. M

    Ryzen: Strictly technical

    Is there any way to make a custom voltage curve and bind it to multiplier? So I can have 1.15V for 3Ghz and 1.35V for 4Ghz?
  21. M

    Ryzen: Strictly technical

    Did you take a look at AGESA 1.0.0.4A updated bios? There are some improvements, among them is better memory support for 4 sticks and faster boot times. One cam wonder what else have been changed. Also, inability to run 16bit software may be dependent as much on host as it is on virtualization...
  22. M

    Ryzen: Strictly technical

    I hope I'm not uneducated but why? Core typically does not know where the required data is at the moment. So it asks L1 Data cache, if it misses the question follows to L2 cache and in case of another miss it will ask L3. Sure, tags are gr8 but they lower typical access time from 17ns to maybe...
  23. M

    Ryzen: Strictly technical

    But weren't those pings between cores? Not L3 caches? So you would have to subtract 20ns from the 140ns score. So to access L3 cache on second CCX you would need about 120ns. From AMD slides L3 was connected to DF and memory was connected to DF (on the other side) - to go to second part of L3...
  24. M

    Ryzen: Strictly technical

    I don't think that would work, because Windows scheduler would place all those processes as it sees fit on CCX0 or CCX1 according to how busy cores are. If I bind all those less important processes to cores from CCX1 then it leaves CCX0 less busy and it is more probable that my game will run on...
  25. M

    Ryzen: Strictly technical

    We could use Process Lasso to bind all those background tasks and programs that are normally running to cores on CCX1 instead of CCX0 and get much better chance of game threads remaining on CCX0 where it belongs, because Windows scheduler will see cores on CCX1 running more tasks so it will...
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