If you were talking to me about the 12LP die shink if you are getting a density increase you can fairly say that they have shrunk the node because everything is PR because fin pitch doesn't really change anymore so all you can measure is the density, to compare it to Intel's 14nm + and 14++ is...
I think going to 6 cores per CCX would offer better performance though and given the work they are already having to put into die shinking ya might as well change the CCX layout while your at it, although the performance delta would only be like 1 - 2% but when I am only looking for a 5 - 7% IPC...
I thought somewhat simmlarly but really think about it, and look at how Naples communicates with the RAM with 4 DIMMS per die it simply wouldn't work with 6 dies which would mean a platform change, also it would mean more pins which is the main reason for the size of the TR4, which would mean...
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