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  1. P

    Question about Core architecture

    Merom (Core 2 duo) is a proliferation of Yonah(Core Duo). But it is an aggressive proliferation! -EMT64 is only supported by Core 2 - Core2 is 4-wide decode/rename/retire vs. 3wide for Core Duo. - Full 128-bit SSEx - Macro-fusion support on Core2. - and much more !
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    New AMD CPU Architecture Announced!

    Did AMD tape out the K8L and do they have some live silicon in their labs? It should take ~1 year from A-0 step to production....
  3. P

    What happend to the Pentium 5?

    Pentium4 was a completely different machine compared to P6 family.
  4. P

    Worth waiting for conroe?

    Conroe is way closer than you think. I say this as someone on the actual design team. And Anand did an honest benchmark.
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    Difference between CPU "Stepping" & "Revision?"

    Depends on whom are you asking. Intel only speaks in terms of "steppings", as Patrick described. Apparently, AMD revisions = Intel "full steppings"
  6. P

    What would a Palestinian state be like for gay people?

    In the best case a gay would be beheaded in the central square in "Palestine". Far more likely for him isto be lynched or stoned to death. Remember there is a "honor killing" culture in Islam: a father/brother can kill a daughter for having pre-marital sex.
  7. P

    Yonah Core Duos are 64-bit?

    Yonah doesn't have 64 bits. Merom has.
  8. P

    AMD's response

    More-or-less true, but there are VERY significant changes in Merom(Conroe-desktop version of it) compared to Yonah.
  9. P

    an honest question about the Conroe vs. FX-60 tests...?

    First of all, I design microprocessors (part of them) for a living.I validated PentiumIV (hence the nick), and then switched to some more adventurous things :-) So, I more-or-less understand, how the things are done ... To get +20% integer performance requires a very significant redesign. One...
  10. P

    an honest question about the Conroe vs. FX-60 tests...?

    From my understanding of the company the situation is as follows: 1. There were absolutely no intention to inflate Merom (this is how the design is called internally, Conroe is a desktop version) numbers vs. AMD. Apparently, ATI chipset for AMD was chosen to allow the same graphics cards on...
  11. P

    Israel threatens assasinations

    Do israel bomb apartments? Yes, we do so. The only known such case to me was killing of Salah Schade( a very serious Hamas bombmaker that was directly responslible for killing tens of Israeli civillians peacefully riding the buses and going to discos). The lack of intelligence lead to death...
  12. P

    IDF 2006 - Conroe Merom and Woodcrest info

    Why are you surprised at the benchmarks? If Core Duo (aka Yonah) was quite comparable clock-for-clock with AMD chips then add on top of that: - 4-wide machine - True 128-bit SSE/SSE2 - Third ALU - and some more improvements. - and all this WITHOUT significant lengthening of the pipe...
  13. P

    IDF 2006 - Conroe Merom and Woodcrest info

    As someone who is actually on a Merom design team, I must say that it was an honest benchmarking that Anand did. There were no strings attached. We've just got a good chip :-) That's all! Merom is, indeed, a NUCLEAR weapon against AMD :-)
  14. P

    Time Person of the Year - U.S. Soldier: For facing bullets in executing the Policies of those that Lead them

    And my Person of the year in 1945 would be Col. Paul Tibbets :-) He won the war on Japanese ....
  15. P

    "Palestinians" attempt to bomb school at Yokneam!

    Original article Quote: A massive security alert in the North was lifted on Wednesday afternoon after the two Palestinians allegedly planning a suicide bombing at a school in Yokne'am were captured by soldiers in the West Bank. The arrests of the two ? both members of the Palestinian...
  16. P

    What's wrong with Israelis???

    Right on, 0roo0roo. Below are some more pictires of Palestinian terror: 1. Ramalah lynching of Vadim Nourezitzand Yosef Avrahami. 2.Dolfi Disco bombing. 21 kids were murdered at 1st of June, 2001. Israel did not retaliate....
  17. P

    What's wrong with Israelis???

    Name: Shalhevet Tehiya Pass. Killed:26. Mar. 2001 in Hebron, on hands of her father that was wounded. See the phto and the article Picture of a murdered girl.
  18. P

    Jewish settlers destroy olive groves

    In this particular case it was proven that the trees were cut by Paestinians ! Frequently, BTW, Israeli Army cuts trees near the roads and demolishes buildings, because they are used by Palestinian terrorists as coverups to attack.
  19. P

    What's wrong with Israelis???

    So-called "Palestinian" authonomy can be safely described as a Nazi regime, with all its attributes. "Palestinian" schoolbooks preach hatred of Jews, and preach genocide of Jews. In Israel there were (or are) peace lessons, where teachers teach co-existence. If Israeli gets into Ramalla, he...
  20. P

    What's wrong with Israelis???

    Israelies want lo live ! This is what is wrong with Israel ! If you know the map of Israel, you may know that the distance from the seashore at Tel-Aviv to the "green line" is only 21km. A good reason to build "settlments" :-) As a matter of fact, if you ever visit Israel, you should know...
  21. P

    hyperthreading?

    Hyperthreading (aka SMT- Simultaneous Multi-threading) would require for AMD to do a complete redesign/revalidation FROM SCRATCH, as opposed to multi-core implementation. The main advantage of hyperthreading is ~30% extra performance for multitherading/multitasking for only ~5% (I may be...
  22. P

    anyone familiar with sse2 and fpu on x86?

    Hello ! If your program requires only ADD/SUB/MUL/DIV/SQRT, and you do not need a full 80-bit precision, then the answer is YES! For a more complex operations, like SIN/COS, you need to emulate the X87 instruction via macrocode. P.S. Keep in mind that on Pentium4 even scalar SSE/SSE2...
  23. P

    what is the high tech difference in the amd vs intel cores?

    Original Pentium/Pentium MMX(P5/P54C/P55C) could execute upto 2 simple instructions per clock, if they could be paired. They were 2-way inorder superscalar processors. Pentium PRO/II/III could decode upto 3 macroinstructions, and retire upto 3 micro-instructions, if conditions are right. They...
  24. P

    AMD with SMT (hyperthreading)?

    While SMT sounds relatively simple to implement, it is REAL HARD to make it work, especially for out-of-order processor. It is quite tough to validate all the boundary conditions and to ensure sane performance and functional correctness. So, I have serious doubts that AMD will do SMT on some...
  25. P

    Asus P4PE & P4PE-L at neweggy.....

    If my memory serves me well, the i845 PE/GE is a new step that improves DDR333 stability :-)
  26. P

    putting more than 1 cpu on a chip?

    Architecturally, x87 FP registers are 80 bits wide. (IEEE 754 extended precision). If my memory serves me well, on IA 64 FP registers are 82 bits wide macroarchitecturally.
  27. P

    HyperThreading - Decoder/Instraction Cache being a Bootleneck?

    << i have read the article about intels HyperThreading. very intresting indid. however it seems to me that there maybe a limting factor utilizing HyperThreading on current P4: 1. Decoder - i've heard that the x86 Decoder on the P4 is being able to decode in a pattern called 4-1-1(4 instractions...
  28. P

    Why Do People Not OC?

    I'd like to divide my answer into 2 parts: why I am interested in OC'ing, and why I don't do it. When people overclock they are basically utilizing system margins. For example, some CPU was specified to run at 1.4Ghz, but can readily do 1.7GHz. If yo've got one, you are lucky. But , in...
  29. P

    How to determine stepping on P3???

    If someone can code in assembler, the following information might be useful. There is a special instruction to get CPU identification : CPUID instruction. Call CPUID (opcode 0F A2, no MOD/RM), EAX=1. The bits 3:0 of the EAX register are the stepping ID, bits 7:4- model id, bits 11:8- family...
  30. P

    P4 or Athlon?

    If you can get an Intel MB for Pentium(r) 4 for a serious discount(including case!), why not:) And a free CPU will not hurt, either:cool:
  31. P

    best way to test cpu stability?

    One proven recipie of finding some stability issues is running multipile copies of XCOPY for a very long file(s). Used to stress I/O quite well :-) Gregory A. Pribush Jr., iMPG. Not speaking for Intel :-)
  32. P

    yeilds vs. clockspeeds - why do chips work at different max speeds?

    << This is something I've always wondered... my tbird 700 was probably intended to be a 1ghz+ part. So, why is it that it doesn't work at 1ghz, but does work at 700 and 800? I could understand that if a chip has a defect it just plain won't work, but how does slowing down make a chip suddenly...
  33. P

    AMD or INTEL?

    I am actually an interested party, and currently have no problems with my BETA Pentium(r) 4. AMD makes some excellent chips, but they have 2 disadvantages: 1. Platform issues. For example, Intel publishes ALL known user-visible bugs since the FDIV days:) VIA did not publish their errata...
  34. P

    Heat Problems with Athlon

    << Put some Thermal Paste on it, the reason for this stuff is to insure that all the cpu area is in contact and conducting heat. Ceramic (what your chip is made of) is a poor conductor of heat because it has microscopic pits all over it that do not contact the metals of the sink or metal of...
  35. P

    Athlon 4, 20% decrease in power, that is way not enough.

    Dynamic power of the CMOS circuit can be estimated by the following formula: Pdyn = aCV^2F, where a is the activity factor, C is the circuit capacitance, V-the supply voltage, F- frequency. Other than the dynamic power (consumed due to switching), there is leaage power. The Fmax depends on the...
  36. P

    Maxtor or IBM?

    I am looking forward to get a new IBM 60GXP... anyone have heard anything about these ?
  37. P

    NYTimes article on Asychronous CPU design

    I do not think it is a wise idea not to use clock gating :-) It is a tremendous power waste. The only excuse for doing so is to simplify the design.IMHO, this may only be considered for the supercomputer CPUs, where cost of cooling is no object. On smaller processes excessive power density...
  38. P

    Answer for this sample A+ question

    Optimum cache size depends on workload and external memory performance. From Hennesy/Patterson, the average memory hierarchy access throughput is: p*cache_throughput+(1-p)*mem_throughput, where p is a cache hit ratio. The same formula is used to calculate the average memory access latency...
  39. P

    Poll: AMD or Intel?

    Intel(R) PentiumIV processor:cool::P:) Especially if you can have one at some serious discount:)
  40. P

    Poll: AMD or Intel?

    Intel(R) PentiumIV processor:cool::P:) Especially if you can have one at some serious discount:)
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