Yes, it's possible that they are over-qualified, but how do you know. My point is that what this guy said is totally wrong, so his conclusion is not credible. Unless there is some other evidence, we don't know whether they are over-qualified.
What the heck are you talking about? I would agree that R&D are not necessarily all PhDs or PhDs are not prerequisite for doing good R&D work. But to say PhDs are just good at documenting and validation is just pure B.S. I bet all major inventions in semicon. (CMOS, MOSFET, FinFet etc.) are...
This whole argument of PhDs monitoring a single equipment is totally false. According to official data from TSMC. Only 4.4% of their employees are PhDs. PhDs are definitely are doing R&D. No freaking way they are "using Ph.Ds to monitor a single piece of equipment on a production line."...
I don't think that's true. According to official data from TSMC. Only 4.4% of their employees are PhDs. PhDs are definitely doing R&D. No freaking way they are "using Ph.Ds to monitor a single piece of equipment on a production line."
I don't think that's true. According to official data from TSMC. Only 4.4% of their employees are PhDs. PhDs are definitely are doing R&D. No freaking way they are "using Ph.Ds to monitor a single piece of equipment on a production line."
But they are probably using master degrees and bachelors...
I agree with you, it's a bit low for Intel.
I'm gonna do an analysis of Intel's logic fab capacity based on currently available information when I'm free. Feel free to check it then.
Console chips are designed to be more defect tolerant, because console chips are low margin business, so AMD cannot afford to just throw away chips with defects. These chips are designed with redundancy, For example, Xbox Series X chips actually have 56CU, but only 52CU are enabled.
So your...
Well it is very tricky to deduce wafer number just from revenue. But Intel enjoys very high margin for their chips. As for TSMC's fabless customers, a very low fraction of actual chip sales contributes to TSMC's revenue (for example Nvidia has a gross margin of more than 60%, which means only...
It happens to the best of us. However this data should be taken with a bit of grain of salt. The figures are a little low for both TSMC and Intel, but shouldn't be far off. For example TSMC nanjing fab (16nm process) started volume ramp to a capacity of 25,000 wpm in 2020, which is not reflected...
Your claim is totally wrong! Even in leading edge, TSMC have much more capacity than Intel.
According to a research by Mizuho securities. As of 2020, the capacity of TSMC and Intel's advanced node are as follows
Advanced node capacity(12''wpm)
16/14nm 7nm/10nm 5nm/7nm
TSMC...
Yeah, that's what I was asking, can you elaborate on this limit, or give us some references.
What's also interesting is how dose IPC scale with processor width n (this width could be decoder width, buffer size, or ALU number or whatever). Do they scale differently for RISC and CISC. For...
Even if there is no limit to ipc. How dose IPC scale with processor width n (this width could be decoder width, buffer size, or ALU number or whatever) is also very interesting. If IPC scale with log(n), even though there is no upper limit for ipc, it will be still a grim future for IPC...
With the end of Dennard scaling, single thread performance is more and more reliant on achieving higher IPC (instructions per second). WIth new techniques we have been able to pushing ipc higher, but it is getting more and more difficult(apple A14 and Arm Cortex has seen diminishing generational...
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