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  1. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    That is a fair remark, albeit a bit removed from discussing CPU architectures and developments among enthusiasts. I equally have no interest in the x86 ecosystem, Windows-based hardware, or RISC-V, but I still like learning about what is happening in the tech market because I am curious about...
  2. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Yeah, that is very obvious. Not sure what these things have to do with each other. You can have great end-user experience and high software quality in a closed ecosystem and you can have total crap in an open ecosystem. Besides, which “open” ecosystem are you talking about? Most of the stuff...
  3. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Law of large numbers is not the right term here, indeed. I'd describe it more in terms of diminishing returns. A more interesting point is what you say about relative vs. absolute value increase. I think we will have to adjust in the future to use absolute improvements more. Expecting consitent...
  4. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Apple has been delivering consistent year to year performance improvements. Apples M3->M4 transition alone is comparable to Zen4->Zen5 in absolute performance increase. I too think that AMD has been making great progress with the Zen family. I don’t see however how their momentum is more sizable...
  5. R

    Question Geekbench 6 released and calibrated against Core i7-12700

    Of course this is a nonsensical result. It is equally as nonsensical to cherry-pick a known (and well understood!) limitation of a test and conclude that all results must be void as a consequence. Benchmarks are not some mystical things, they are well-studied, and mostly understood software. Any...
  6. R

    Question Geekbench 6 released and calibrated against Core i7-12700

    Cinebench R23 is a benchmark of SIMD throughtput and L1 cache bandwidth. It's as useful for assessing general CPU performance as someone's love of pizza is indicative of their knowledge of the Italian language. The 2024 version is barely any better. The only reason why Cinebench kind of works...
  7. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Which is why compares across multiple results to quantify uncertainty. It works, even if the individual results are unreliable. There is no doubt that Anandtech results are more accurate per measurenment, they are still a single number which fails to capture the variability inherent to these...
  8. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    And I have seen power consumpion of M1 at around 5 watts (3.2Ghz) and M4 at aroudn 7 (4.05 Ghz). So their M4 results I can agree with, the M1 strikes me as extremely low (incidentally i see 3.25 watts when more than one thread is active and the M1 core is runnign at 2.7Ghz, so maybe that's the...
  9. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Given the variability in the results and how sensitive they are to external factors I don't trust point estimates anymore. Just a 100Mhz clock difference can have a massive effect on IPC estimation (e.g. given a score of 11 points 3 Ghz vs 2.9 Ghz give you 3% difference in IPC!). That's why if I...
  10. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    It was around 5 watts for M1, it is around 7 watts for M4. Let's say 50% increase. Looks bad on paper, until we remember that these are sub 10 watt cores. I'd say they have a problem once they need to raise the wattage past 12 watts per core. Until then they are fine. Which CPU runs at peak...
  11. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Maybe it’s time to put this argument to rest? In the last 4 years Apple had more ST gains than any x86 designer, and their rate of improvement actually accelerated with M4. Yes, some of those were achieved by increasing the power consumption (just like anyone else does). There is no evidence...
  12. R

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    “IPC” depends on the workload, and I think it would be good to discuss it as such. Looking at GB6 subtests, M4 improved iso-clock performance between 0% and 30% (this is discarding tests that benefit from the new matrix hardware). In the few sub tests where the iso-performance did not improve...
  13. R

    Discussion Apple Silicon SoC thread

    Different functional blocks, optimized for different purposes. The GPU is least specialized (and least efficient), the NPU is most specialized.
  14. R

    Discussion Apple Silicon SoC thread

    I only tested the P-core SME, single-threaded. The E-core should add another 25% I think (don’t quote me on that though). SME also has this weird 1-bit “matmul”, haven’t had the chance to test it yet.
  15. R

    Discussion Apple Silicon SoC thread

    I am getting 250 GFLOPS (FP32) doing vector FMA on M4's SME unit. The hardware is, in principle, capable of 2TFLOPS, but there is not enough register file bandwidth, which means that you are limited to 2x 512b SIMD slices out of the available 16x. If Apple cares about vector performance, they...
  16. R

    Discussion Apple Silicon SoC thread

    You mean high throughput and high latency, right? That’s interesting! Do you have more info on this?
  17. R

    Discussion Apple Silicon SoC thread

    It is true, to a certain degree. We do observe some power inflation since A12. For example, M4 cores seems to use ~7 watts compared to M1's 5 watts. Some have interepret this as stagnation, others see it as a transition from a smartfone-focused core to a more desktop-focused core. Also, it's...
  18. R

    Discussion Apple Silicon SoC thread

    I wish I had their blind faith :D BTW, this is M4 compared to Zen 4 iso-clock (without Object Detection). That's quite a distance to close for team red. P.S. And just for fun, this is the same comparison between Zen4 and M1. Turns out they have identical IPC! In GB6 Blur subtest at least...
  19. R

    Discussion Apple Silicon SoC thread

    Is the messiah Zen 5?
  20. R

    Discussion Apple Silicon SoC thread

    What happens in two more days? SME is a fairly usable vector SIMD unless you need flexible permute. 250 GFLOPS vector FMA/cluster is nothign to sneeze about. How come? Aren't they leading the industry in pretty much every single SPEC subtest?
  21. R

    Discussion Apple Silicon SoC thread

    Exactly. Apple essentially merges the "traditional" CPU L3 into L2, between-cluster communication is handled via the SoC-level cache from what I understand. A meaningful comparison should also consider the architectural differences. Apple's CPU cluster essentially plays the same role as AMD's...
  22. R

    Discussion Apple Silicon SoC thread

    Erm, Zen4 has what, 1MB L2 cache per core, and M2 has 4MB? Of course Apple ends up being slightly larger, SRAM is not free. The M2 P-core core itself (sans cache) is practically identical to Zen4 at 2.6mm2 (which is interesting if one considers that Apple has wider arch, more L1, and much...
  23. R

    Discussion Apple Silicon SoC thread

    8 out of 15 GB6 subtests show 5% or higher iso-clock improvement just from M3 to M4, four subtets over 10% improvements — this is excluding SME. Didn't look at M1 vs M4. I think the improvements are there, and they are decent, it just becomes much more nuanced. Again, Apple is so far ahead in...
  24. R

    Discussion Apple Silicon SoC thread

    Or maybe it's just difficult to make good IPC increases if one already leads the market in IPC by a large margin. I don't think the "lost team" argument has much merit. Apple is still delivering very good performance improvements, and they have had substantial IPC improvements (just not on all...
  25. R

    Discussion Apple Silicon SoC thread

    It will use the NPU if you give it a stuitable CoreML model. Most popular frameworks do not use that functionality.
  26. R

    Discussion Apple Silicon SoC thread

    Well, whoever added it to the WIkipedia is wrong. Quite a lot technical details on Apple Silicon is wrong there. And the funny thing is that it is impossible to correct this information because no definitive authority exists. Basically, whoever edits the article first gets to invent whatever BS...
  27. R

    Discussion Apple Silicon SoC thread

    As I said, I don’t find it reasonable that a CPU draws the same amount of power reading a spreadsheet as it does running a demanding multicore compute job. This is not good user experience.
  28. R

    Discussion Apple Silicon SoC thread

    I welcome it when a CPU uses up the entire available thermal range, but this has to stay within reasonable limits. I do not think that 50+ watts for single-threaded operation is reasonable. A desktop might get away with it (even though it's a massive waste), but it is simply unacceptable for...
  29. R

    Discussion Apple Silicon SoC thread

    I would say that the distinction between SME and SSVE (or between SME and SME2) are purely technical. What’s important to me specifically is that I have a bunch of instructions available in the streaming mode, and those variants that either accumulate to Z registers or to ZA slices. The...
  30. R

    Discussion Apple Silicon SoC thread

    It's not a silly guess and Maynard is right. SME does have vector instructions that put the results in the ZA storage and usage them give you roughly 8x improvement over base SSVE versions. It's the nature of the AMX unit — the ALU is associated with the matrix storage, not vector storage. It is...
  31. R

    Question Incredible Apple M4 benchmarks...

    Thank you! You are right, I should have paid better attention. I full agree with everything you say here.
  32. R

    Question Incredible Apple M4 benchmarks...

    That is very possible. Could you be more specific?
  33. R

    Question Incredible Apple M4 benchmarks...

    I have no idea, I don't work for Best Buy or for Apple. I prefer to make my own judgements based on information I can find and tests I can run myself.
  34. R

    Question Incredible Apple M4 benchmarks...

    What the heck is that and what channel is it on? What do best buy product categories have to do with Apple marketing?
  35. R

    Question Incredible Apple M4 benchmarks...

  36. R

    Discussion Apple Silicon SoC thread

    Pretty much this. I did scrape a few thousands results some years ago, and it was a drag. Luckily, they've you the possibility to access results as neatly formatted JSON, but you need to login to do that, which makes it hard to automate. I'd probably need to write a browser extension for this...
  37. R

    Question Incredible Apple M4 benchmarks...

    The newest version (Cinebench 2024) has increased the scene size so that it does not fit in the cache of the most CPUs, and they also fixed a performance issue with their AVX emulation on Apple CPUs. And of course, the newest Cinebench is being heavily criticized because suddenly Apple Silicon...
  38. R

    Question Incredible Apple M4 benchmarks...

    Correlation beween SPECInt and CB r20 results is purely coincidental in that they share the same confounder: CPU frequency. CB r20 is essentially a benchmark of L1D bandwidth + SIMD, and the CPU models you are looking at did not have any large changes in that domain.
  39. R

    Discussion Apple Silicon SoC thread

    I don't think that dealing with outliers is the biggest challenge. Scraping the results is probably the most annoying part IMO.
  40. R

    Discussion Apple Silicon SoC thread

    AMX unit also accelerates the vector algebra routines and it was previously much faster than these new results. Notably, their result is consistent with the use of single accumulator. I looked at the code and they use the Zx registers, maybe one gets better performance by using the ZA array as...
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