Instead of varying or heavily cutting(like in 6600u vs 6800u)the igpu CU count on a chip to differentiate products would it not make more sense now to just have a very small L3 cache for base models and use cache chiplets for the premium models?
2-4mb L3 for the office pc apu and 64mb chiplet...
Doesn't backside power delivery make putting the cache chiplet below the apu chip possible? It seems me that the ability to put the cache below the apu for heat reasons and a unified L3 are the two big developmental hurdles to cheap and powerful APU's.
When/if these two technologies get...
As long as there is excess wafer supply and lowering the profit margin would be recouped or better with higher sales the price will be lower. As long as an APU is cheaper to produce than its equivalent discrete cpu and gpu counterparts(which is often the case) it will be sold on average for...
Not to mention that the phoenix APU will have at least as many, and up to 50% more CU's than the 6500xt which, like the replies above pointed out, is bandwidth constrained even with 4GB of gddr6 and 16mb cache exclusively used by the navi 24 die, and strix point will surely have significantly...
The problem with chiplets is their power draw is higher, particularly idle power draw. Its only a few watts extra and doesn't matter too much for desktop applications but it is not really viable yet for mobile. In a way, a cache chiplet similarly frees up space to a regular chiplet design but...
Its a real shame prices are going up from a combination of inflation and increasing design/wafer/process costs because the Zen5/8000 series strix point APU's have the capability to finally overcome bandwith limitations and push up the base level of computing and graphics processing power in the...
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