https://patents.google.com/patent/US11435798B2/en In this new patent from 2021, Apple introduced adaptive DPE which compares the estimated value with the physically measured value and adjusts the weight in accordance with the error. So the quality of the estimated number is quite good(especially...
The reason why I put the dotted line in the scheduler blocks is that I don't have enough time to set up all the test patterns and figure out each scheduler’s entry count(only 2 days). But Maynard Handley pointed out that two schedulers that are side by side can share instructions in certain...
Both although not a way to find out the actual pipeline length with software methods. People mostly use branch prediction penalties to estimate the pipeline depth but in recent days processors have heavily optimized the latency of the branch instructions(by passing for example); In addition...
Here I meant that Apple is facing what others will face once they reach a certain point in the future. Also, IPC depends on pipeline depth, so this is more like a trade-off. When you have a deeper pipeline it's usually easier to achieve higher frequency and thus higher performance, but the...
Yes, just like everyone else.
I think not, they will keep tweaking the current architecture(e.g. enhancing the register file design, better utilization of the functional unit, increase the size of various structures). Ultimately the answer depends on what you mean by "massive core redesign"...
For Apple is impossible, for Zen5 I wouldn't say 100% impossible, since their baseline is not that high, and by playing some tricks on the "standard" of IPC. If you look at the research papers in recent years(10 years or so), you will find that they are all focused on tweaking the current...
Maybe Apple just changed its naming convention, maybe they decided to stop exposing their microarchitecture name...etc I don't know. Also, apple names its SoC with a format like Txxx(T6000, T8020etc). Once I checked Apple's device driver tree for the iphone15 pro, surprisingly its P/E core used...
Yes :), I also helped them to test branch prediction and core-to-core latency on m3, though not many had found it lol.
We all Stand on the shoulders of giants.
Yes, but it takes time. Maybe I should wait for the next Apple silicon release.
Late reply, but you can. I helped them do the reverse engineering on the A17 pro, I used various ways to measure the size of different structures and identify different types of functional units. junjie1475/iOS-microbench (github.com) Here is the code I used to reverse engineer the A17 Pro. But...
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