There is something wrong with those clocks because the averages are 4400 for the first result and 4390 for the other ones. It's a 0.2% difference.
So, most results between 2500 and 2600 are valid and not throttled.
There are some weird scores (less than 2400 and more than 2700), but they are...
Here are a dozen of the latest Geekbench results for Apple M4. I don't see 2700-2750 there. The regular scores are closer to 2500-2600.
2700-2750 were probably obtained under LN as Geekerwan did.
Also, there are some results for Geekbench 5. The P-core in Intel Core 285K matches the one in Apple M4:
That's not a fully fair comparison because of the Geekbench Windows tax, but it is pretty interesting.
There are some new Geekbench v5 and v6 results for Arrow Lake:
https://browser.geekbench.com/v5/cpu/22777737
https://browser.geekbench.com/v6/cpu/7341479
It looks pretty nice.
You can always adjust PL1, PL2, TAU, and many other settings to match your preferences. Power limits are not fused into the CPU, even on laptops.
I hope that Intel and OEMs will add the Undervolting Protection setting to the BIOS for the Arrow Lake H and U series. HX has that, but it's hidden...
Arrow Lake is expected to use a very similar topology to Meteor Lake.
Meteor Lake is probably below the initial Intel's targets, but it's pretty good in terms of battery life and power consumption under light loads:
~10-20 hours under the Notebookcheck's web surfing test is a good result...
It looks like the hype train has crashed. We've never seen that, and here it comes again :p
From my perspective, Zen 5 looks fine, especially on mobile devices. I hope we will get the X3D variants soon.
Unfortunately, I don't have accurate data for 14th-gen ST power consumption. We need to keep in mind that 14900HX is three major nodes behind (10nm vs. 3nm), not to mention sub-nodes like N3B and N3E. Arrow Lake is expected to be much more representative here.
Those settings (AC/DC Loadline...
Because the CPU power characteristics depend on a lot of settings and microcode optimization.
My favorite examples are Dell Precision 7670 and 7770, which suffered severe performance issues because of the incorrect IA AC/DC Loadline values. This issue was fixed 6-7 months after release...
I use 125H with 4.4GHz because it has a lower PL1 (28W). Even in this case, a single P-core uses nearly half of the PL1 limit. That was the initial point.
Obviously, power limits and the power configuration depend on the OEM and can even be dynamically adjusted by the system.
Returning to...
Nope. Meteor Lake uses 15-17W (Package Power) under the ST workloads on 4.4GHz. If we decrease the frequency to 3.6GHz, we will get 9.6 to 10W (link).
The results on the newer node are expected to be much better.
Ultimately, the only thing that matters is the absolute performance at a certain power consumption. There's nothing wrong with Apple stagnating with gen-on-gen IPC uplifts while the power consumption is under reasonable limits. Apple M3 Max in MBP16 consumes ~70W under CB R23 MT load. It's...
The P-core in Apple M4 consumes 5.6W at 3.87GHz and 9W at 4.46GHz. If we assume that the P-core can achieve 5.1GHz and consume 16W, the power consumption literally tripled for an additional 1.2GHz or 30% higher clocks. If we consider the architecture width, the P-core in M4 consumes 6% more...
There are many reasons why we won't see Apple M-series CPUs in servers anytime soon.
In the server market, many factors matter much more than performance. These include the software and hardware ecosystem, relationships with OEMs, upgradeability and maintainability, and others.
Even AMD is...
It's an engineering sample. The clocks and power consumption are not final and will be optimized.
If we get a 3% better score for Arrow Lake running on 4.7GHz than Raptor Lake on 5.4 - 5.8GHz, it's a great result (~15-20% ST performance increase)
It appears that Jaykihn's results, which showed a 3% ST and 15% MT increase, were obtained on the 4.7/4.0 GHz clocks:
Obviously, the retail CPUs will use higher clocks.
Lion Cove was optimized to be more performant at lower power limits; its performance/power curve is steeper at the beginning and quickly becomes saturated. It's closer to the typical AMD Ryzen curves, where, at a certain point, there is literally no performance improvement regardless of the...
I do not think there will be any significant changes to the compute tile. It will still have an 8+16 configuration in the top desktop SKU.
The Arrow Lake Refresh will bring the updated SoC tile. It will probably have a bigger NPU and some changes to the memory controller and media engine...
Actually, AMD has constantly featured different versions of Cinebench in its presentations since Zen 2. Also, Qualcomm featured results of this benchmark during the X Elite announcement.
Cinebench R23 and 2024 tend to show good results on all platforms, including AMD, Intel, Apple, and even Qualcomm.
According to the Chips & Cheese research, the AVX-512 usage in Cinebench R24 is close to zero:
In general, Chips & Cheese considers Cinebench R24 as a more balanced benchmark...
Geekbench 6 is not that different here as well. Let's take a closer look on the technical details of the tests included in Geekbench 6:
1. File Compression
Almost useless. Instead of LZ4 and ZSTD, it makes sense to use deflate (gzip/zip), which is used everywhere on the web and system-wide.
2...
Yes, it will be challenging to implement, but Intel may find a solution.
The current engineering samples of ARL-P, PTL-U, and PTL-H are being tested with the LPDDR5X memory kits. They are marked as T3 and T4, but I'm not entirely sure what it means.
I do not think that PTL-U will use the on-package memory. PTL-U has the U letter, not V.
The new SoC tile in PTL and ARL refresh will probably support both LPDDR5/5X and LPDDR6, as we have seen with Alder Lake and DDR4/DDR5.
Intel needs Lunar Lake for a few reasons:
1. Have a platform with the...
I added a credible leak to support my claim ;)
Let's analyze that chart closely. Intel is going to update the pinout for PTL-U and PTL-H. This platform will be released in 2026 and actual devices will appear in Q1 or Q2 2026. The following platform released in 2027 will use the same pinout as...
Panther Lake is a 2026 product that is not Pin-to-Pin compatible with Arrow Lake, according to the recent Clevo's leak:
I don't see any good reason to change the pin layout for Panther Lake and then change it again for the LPDDR6 support in the next platform a year later.
Intel will probably...
Panther Lake will use the 192-bit LPDDR6 CAMM2 memory (8x24 bit).
There's no option to use the old 128-bit interface (8x16-bit) because LPDDR6 has 24-bit channels:
Intel Lion Cove has 33% more peak throughput than Raptor Cove (8-wide vs. 6-wide), but in the real apps, the IPC increase will be closer to the values presented by Intel (10-20%).
Obviously, some apps will be able to utilize all the throughput and show ~30% increase in performance (as we see on...
It's pretty weird to see 20-30% IPC claims. Intel has given us some first-party numbers:
It makes sense to expect similar numbers for P-cores in Arrow Lake vs. Raptor Lake.
Also, if we take a closer look at Lion Cove's performance/power curve, we will see that it's steeper at the beginning...
I guess we will get similar Crestmont cores. Probably, they won't be exposed to the system.
I think Intel would like to use the SoC from Meteor Lake in Arrow Lake, but it won't match Microsoft's 40 TOPs requirement. So, Intel probably has to make some changes to the SoC tile. Maybe we will get...
The performance impact of moving the IMC to the SoC tile will be minimal (0-5% IPC). Here's a comparison of Raptor Lake (13500H) to Meteor Lake (125H):
It appears that both the desktop (ARL-S and ARL-S) and mobile (ARL-H) will have LP-E cores. They are not necessary for desktops but might be pretty useful for ARL-H and ARL-HX. The same can be said about two embedded TB4 controllers.
It looks like Intel is going to make ARL-HX more...
Lunar Lake has mostly the same structure, including NOC fiber, LP E-core island, separated GPU, IO controller, separated memory controller, etc. The most notable difference is the way the P-core cluster and the Side Cache are organized.
At the same time, the physical implementation is...
Lunar Lake is similar to Meteor Lake (with the differences I described earlier), but with three tiles fused in one to save power.
Lion Cove cores in Arrow Lake can offer a higher IPC because of the bigger L2 cache and lower memory latency. But the difference is pretty small. I expect it to be...
With the tiled approach, Intel has to separate the memory controller and put it into the SoC tile, as we have in Meteor Lake. There are no other options. Intel will probably also put some hidden LP E-cores in the Arrow Lake SoC tile. At least it makes sense for ARL-H and even HX.
I was...
I have found a slide from Intel:
It looks like Arrow Lake will have a similar structure to Meteor Lake, with an NOC, a separated memory controller, and other stuff (aka the new approach).
Yes. Meteor Lake suffered a problem when two LP E-cores weren't powerful enough to perform most of the...
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