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  1. Y

    ILP and instruction dependencies in the x86 ISA

    Hello. im a n00b in micro architecture (I do have basic understanding of Piplines, BUSes, branch predictions etc) - but would very much like to get a deeper understanding of instruction dependencies in the x86 ISA so I can use the knowledge to write a decent article about the Hammer architecture...
  2. Y

    Why Hammer doesn't need FSB?

    in a MP congiration Hammer system each processor is assigned dimms of memory to comunicate with. if a given processor asks for a memory adress that itself isn't connected to then the request goes through a HyperTransport to the processor that can comunicate with the memory module which holdes...
  3. Y

    Why Hammer doesn't need FSB?

    as mantioned above the defanition of the front side bus speed is the speed in which the CPU comunicates with the core logic, core logic being the north bridge. sence the memory controler is on die, you can think of the front side bus as being the CPU speed. i've heard from an AMD employ (on...
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    I need a good PHP/MySQL book - Please help me select

    I've seen many books at amazon and I really cant chose! some cover more PHP with litle MySQL some the other way around... some look good and popular, but the best books i've read aren't that popular. so I need advice from some one who actually already studied PHP/MySQL I need to get a data...
  5. Y

    HTs take on the Future of CPU rating

    True ? I used the EV7 in-order to emphasize the problem and to avoid making compression between competing products in-order to keep the debate at the technical level and unbiased.
  6. Y

    HTs take on the Future of CPU rating

    You know the subject so I'll make it short: What's your thoughts of future CPU rating ? its obvious that the public won't go read benchmarks before they buy a CPUs ? and MHz alone should stop being considered as an absolute rating of a CPU. And its clear why: the average person would pick up a...
  7. Y

    Hammer - 67 Million transistors - 103 mm^2 die - how?

    Thanx For all the answers. :) always thought that the number of transistors has liner relation to die size... well... I better dig up some more on CPU design and stuff :)
  8. Y

    Hammer - 67 Million transistors - 103 mm^2 die - how?

    Here's an interview with Jerry on AMD. Intresting read. here's a quote from jerry I can't quite figure out: " The Hammer, which is an eighth-generation processor, is 103 square mm, versus our seventh generation, which is 80 square mm. [There are] 67 million transistors in the Hammer?67...
  9. Y

    Did any Pentium 3 DDR based mobos ever came out?

    is there such a motherborad for sale (or was) ? any dual P3 DDR-SDRAM based mobos out there? thnx
  10. Y

    How do I get Myself a Good forum?

    << You might want to start out with an EZboard or some other free host at first if you're really new at this, but there are several pl, cgi, dhtml free forum codes availible if your server supports the language. I use a UBB forum on my site, and it works out well, though I don't think they're...
  11. Y

    How do I get Myself a Good forum?

    HI! im thinking of starting my own Hardware site (just a local site - not competing with anandtech :) ) any way, I have a crew and all and I know HTML pretty well. all I need is a forum and maybe some CGI scripts for a news system. the problem - I dunnu anything about CGI I need somthing that...
  12. Y

    ClawHammer Logo (pic) !

    Sue me? Are we talking about the same company? little old jolly Christmas green AMD? to sue? Me?
  13. Y

    ClawHammer Logo (pic) !

    THE LOGO! ok maybe I just made this one up myself... but how about a Hammer logo contest? I bet you can do better then me!
  14. Y

    do Diffrente processors gain Scaling diffrently (in %) on the same processs shrink?

    Thank You! not only this was a great explantion - but it turns out I was sorta right! BTW could you explain exeactly what are gate and interconnect delays ? now I think I now some of this : like Gate delay has to do with how fast the gate switchs... but Im not sure. and I know nothing on...
  15. Y

    do Diffrente processors gain Scaling diffrently (in %) on the same processs shrink?

    Im having a bit of an arguement on this. my friend says: << (assuming the quality of the .18 micron processes are the same((copper etc etc)) And chip A: Tops out at 1.5ghz While chip B Tops out at 3Ghz. If you Drop them both to .13(again same process) and chip B Now tops out at 6ghz Chip A...
  16. Y

    How Many CPUs can AMD Make?

    Thank You! hmmm 50 million a year... maybe i'll pay Germany a visit over the summer holiday... 50 million, think they'll miss one?
  17. Y

    How Many CPUs can AMD Make?

    Sorry about my english im form Israel...
  18. Y

    How Many CPUs can AMD Make?

    Will it be able to control much greater market-share then todays 20% ? what is the current Dresden fab utilization ? I think these are big questions for AMD... any insights are welcome. Thank You!
  19. Y

    PM's take on the Intel Article

    Intel Makes good ALUs in fact - they make very very good ALUs! darn right amazing ones! low power low leakge extremly fast! kind of bad thier current microprocessor arcihtecture isnt even close to be as good or sufficent to feed thier fantastic ALUs... im not joking about it - most of what...
  20. Y

    Hammer, The Chip To Break or Make AMD?

    As I see it the K-8 is AMDs Chance to get the approval it deserves and for ever leaving the image of being second place and a follower to Intel. Performance was never the problem for AMD since the Athlon. Poor Media coverage & public awareness, notorious VIA chip-sets complains (some legit...
  21. Y

    why would you need to recompile code in order to execute it at 64bit?

    ok - say you have a 64bit processor that uses 32bit adresing would you be able to do the jmp as one micro-op? if you can - then 64bit adressing just killed all the preformance benfit...
  22. Y

    why would you need to recompile code in order to execute it at 64bit?

    As I understand a CiSC 32bit processor takes instruction at various sizes and divides them into 32bit RiSC like instructions to be executed in 32bit execution units. A 64 bit CiSC processor can execute 64bit instructions hence he divides complex instructions into 64bit RiSC like instructions...
  23. Y

    Not sure if this is HIGHLY TECHNICAL, but whatever...

    Volteage -> rise it to specifications its 5AM
  24. Y

    A Bunch of Hammer Info as well as *Confirmed* Hammer News. Intel's Secret "Yamhill" Project.

    << Ok, but I think he just showed you the error in your original assertion in your previous post, at least give the guy some credit that he's right instead of sidestepping the question and acting like the whole line of discussion was moot anyways... Also, on the question of memory...
  25. Y

    2D Filters and Image Quality - how does that work?

    ok... i know the piplines the TMUs Memory Bandwith and memory controllers in conjunction with Video card. but what about somthing more then mere preformance&Brute force...? what about the 2D Filters on Video cards how and what do they have to do with Image Quality? this piece of knowldge i...
  26. Y

    HyperThreading - Decoder/Instraction Cache being a Bootleneck?

    i have read the article about intels HyperThreading. very intresting indid. however it seems to me that there maybe a limting factor utilizing HyperThreading on current P4: 1. Decoder - i've heard that the x86 Decoder on the P4 is being able to decode in a pattern called 4-1-1(4 instractions...
  27. Y

    HyperThreading - Decoder/Instraction Cache being a Bootleneck?

    i have read the article about intels HyperThreading. very intresting indid. however it seems to me that there maybe a problem utilizing HyperThreading on current P4 which: 1. Decoder - i've heard that the x86 Decoder on the P4 isnt that good... being able to decode in a 4-1-1 format (4...
  28. Y

    AMD 0.13SOI and Motorola/AMD HiP7(good read), questions about transistors in general.

    << When you say "efficiency" what is the efficiency you are looking for, and relative to what previously? Power? Speed? Some of the factors that affect transistor performance as transistors shrink include: * leakage currents as a proportion of total current * operating (core) voltage *...
  29. Y

    AMD 0.13SOI and Motorola/AMD HiP7(good read), questions about transistors in general.

    I came across an article about Motorola/AMD HiP7 process, and they seem to know there stuff and are also pretty excited about it: However?is the currently planed AMD?s 0.13SOI process (Barton, Hammer) is actually this HiP7? And ? what kind of factors, except gate length, effect the overall...
  30. Y

    Some questions about the Hammer Integrated memory controller

    << From the Anandtech article on the technology behind the Hammer: << Thus the Hammer architecture calls for an integrated memory controller (MCT) and an integrated DRAM controller (DCT). The memory controller is a generic interface between the Hammer core itself and the DCT; this controller...
  31. Y

    Some questions about the Hammer Integrated memory controller

    Its My first post here so I dunnu if this belongs in CPU or highly technical? (Kinda Posted in both, sorry :o ... we don't have forums of this level in Israel?). How can I generally think of FSB on the hammer? Is the hammer memory controller capable of accessing the memory for each CPU clock...
  32. Y

    Some questions about the Hammer Integrated memory controller

    Its My first post here so I dunnu if this belongs in highly technical? (we don't have forums of this level in Israel?). How can I generally think of FSB on the hammer? Is the hammer memory controller capable of accessing the memory for each CPU clock cycle?? Will the hammer require any...
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