1.4Ghz at launch and they expect to sclae it 1.2Ghz in less than a year!! One AMD has a killer chip Intel has no answer to or the people who make the roadmaps are full of BS. Figure Intel with the 20 stage pipeline in the P4, the perfect 180nm to 130nm switch only scaled the P4 1 Ghz in a year...
Another thought about HDD performance why not include DIMM / SO DIMM slots on it for an expandable buffer? forget this 2-8 meg tiny buffer garbage how bout a 2-8 Gig Buffer tat you decide what files get cached.
I have an old gateway model mumber P5-200, it has a 256K Cache Module can this be replaced with a say larger Cache Module, this is just for fun to see if i can get it to run Xp Pro.
PC800 RDRAM has a 40 ns latency, PC1066 32ns, PC2700 DDR, is between 6/7ns that is between 1/5-1/7 of PC1066 RDRAM's. RDRAMs only advantage is it queue memory transactions.
Jeff, granted the 2800+ will be cheaper when it comes out, or should I say "IF the TBred B version of the 2800+ comes out?"
Plus if you read the reviews fully you will notice the 2800+ are on the NForce2 a board thats still not on shelves, without the Nforce2 the 2800+ looks like crap.
With...
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF
Pages 29-37 point out what i am talking about, the page 45 show unloaded latencies under ideal conditions.
my question is how much will the dual channel DDR controller offest the queues to access the memory of other chips in the systems according to AMD PFD in 4 way system they look pretty steep.
If its Vans it is 100% Anti Intel no matter what.
If AMD had included SSE2 in the Tbred core non of this would be an issue.
AMD's goal is to get it base of user to think that bapco's and other benches hide AMD's true performance so even if its only on par on the benches it must be even better...
Has anyone seen the portable dry ice makers? All they are is a can of co2 feed into a metal box under pressure right.
Why couldnt someone do that for PC case cooling?
BlvdKing:
exactly the test Bapco included are 128 bit double presion FP operations that can take advantage of Intels SSE2.
Thus if AMD included SSE2 it wouldnt matter, AMD just wants to cry and whine like they always wrogned then when the include Intels op coded people still think the benches...
First Hammer will bench the same as the P4 due to the addition of the SSE2 op codes being included. AMD could have included SSE2 in Tbred and it is covered under the current cross licencing agreement so they had no reason other than to cut cost not to include it.
So AMD has made it a point to...
With the TBred B core adding a layer to the chip what advantages / disadvantages does this cause?
Granted lower heat/ power requirments is common sence, but what else does it offer or cost?
Like I was saying SSXeon.
This is why Itanic is so powerful in its native state. But once it have to do a decode for an x86 instruction it curls up and dies, becuse it doesnt need massive decoding units like all current x86 chips.
The issue isnt clock speed but chip design, at higher speeds the chips decoder units cant keep pace, 1/2 the P4 core(not counting caches) is decoding units.
Decoding units make up most of the core of the chips, the reason the P4 is so huge and scales so well is massive decoding units can feed...
I dont get why everyone here is saying 64 bit for memory addressing, becuase hammer uses Xeons 48/40 bit addressing, not a true 64 bit memory addressing system. The xeon 48/40 bit addressing setup supports 280 TB of ram where a real 64 bit soultion would support 18,000 TB.
On board not on die. hammer will have a lanecy advantage. for X86-64 to work AMD has to actaully support compliers for it not hope Intel does for them like with MMX and SSE.
Plus x86-64 software will be a rarity in the destop market for the first 2 years of launch in the 4-8 way MP it will not...
me spreading FUD I am quoting AMD's white papers how is that FUD?
your the one who is spreading FUD Clawhammer wont have 512K L2 cache. 2% of die space is x86-64, they are op code not a full instruction set hence it is like Intels MMX/SSE/SSE2. SSE2 accounts for only 2% of the new core space...
actually the P4/P5(?) switch will be at about 3.2 Ghz not 3.5Ghz or 4Ghz.
Plus if the K7 scales so well why at the .13 micron process hasnt it hit 2Ghz? come onTbred has been cooked my friend with water cooling only got a 200Mhz OC where he could get a 600 with his Pally core. see at the 130nm...
alexruiz It clearly shows the Intergrated northbridge has 3 Ht links, Page 26. why?
One for the AGP tunnel, 1 incase a MB maker wants to use an off die memory controller and a 3rd incaes they want PCI-X, 3GIO, or RapidIO, along with PCI.
Joe: also the P4 is a totaly different beast single 20 stage pipeline. REE, and other features greatly seprate it from the P3.
AMD has alwasy tried to make a chip last longer than it was designed to remember when AMD said there was no need for a 386 becuase they added Mhz to the 286?
there...
Joe:but completely ignore the P2 to P3 transition where the P3 at the time was just a P2 with SSE and the oft-ridiculed processor identification number.
you forgot to mention the full speed cache, going from non blocking 512Mb or 4 Gb cacheable to non blocking 64 Gb cacheable. Plus the read...
Bransford: its an AXP core with a 3rd FP pipeline and the pipelines have 2 extra stages so hammer will have a 12 stage ALU and 17 stage fpu and an improved TLB. .
Also IF the on die MC is use better latency, but it can be disabled but why when the AXP core is memory senstive to latency?
Its...
BuddyAtBzboyz, but how much does the P4 have of the P3?
It can sacle well into the multi Ghz range it has a single pipeline, it is a totally new chip, AMD says hammer is an AXP core with additions AMD has never made its own "NEW" core the athlon was taken fron NextGen when aquired not made by...
The extra pin are for DDR, bios updates should be no problem because my old gateway worked fine with MMX even though MMX wasnt even know about when the board was made and i had never updated the BIOS on that sucker.
Like this one that show 3 seprate Ht links?
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/MPF_Hammer_Presentation.PDF
oh and HT isnt a FSB because each transaction is put on a list then excuted so it takes even longer to access the DRAM hence 20 Entry MCQ.
So now you graphic...
its just like the K6-II to K6-III.
They slightly modify the core slap a new name on it and they have "new" core, when its clearly based off the old one.
Its still faces the same limits the old one does.
http://www.geek.com/news/geeknews/2002Jul/bch20020705015267.htm
AMD is still pushing High...
Hammer wont be blessed with a huge cache. AMD intergrated the whole northbridge into the core of the chip, ya that chip thats 1/2 the size of your processor with the passive heat sink on it that stuck to you MB.
Hammer isnt really anything new just a reworked Althon for the 3 or 4 time.
no one has adessed hammers true size here its funny.
Think about this for a minute.
Notice how big your northbridge chip is on your motherboard? Most of the northbridge in in Hammers core plus three seprate HT links for chip to chip communication on the die too.
Granted most chipsets arent...
Ok some of you have read my post and you know i am not a totaly idiot but i am going to be biulding my first system from the ground up once I get my settlement about 2 monthes from now.
here is my debate I am tired of my pc but I hate getting locked out of upgrading so should I wait for a board...
Exactly the 146mm chips where so good that 2.4 Ghz chips were overly common why waste money making a larger chip than needed for idea yeilds. Thus make it smaller and make the same money per chips and yeilds of higher chips drop a little but profits are higher becuase you can get a few extra...
SSXeon
Thanks I have only been around PC's sence 1996 my mother bougth a gateway i was 13 at the time so I used it to play games and learn more about computers from sites like this and over time i have pick up some stuff here and there,
but the is a lot I dont know I wish I knew it all like the...
Exacty mech I could see the space to disappate the heat is the same w/ or w/o the IHS. So the core size is still important to transfer the heat away. BBUL could help by allowing Intel to spread the chip out some inside the package and allow the to configure more speciality processors but then...
http://www.sandpile.org/impl/p4.htm
also there was a news post on ZDnet a while ago about its smaller core.
I was talking to people about why the Tbreds were not OCing like expected and i was talking thermal loads per mm^2 and the light went off that intl shrunk the P4 some because of its...
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