So, I made this post to collect all the die area numbers of various smartphone chips.
With such a list, it is easier to compare the chips and provides some interesting food for thought.
Apple
A15 Bionic - 107.7 mm²
A14 Bionic - 88 mm²
A13 Bionic - 98.48 mm²
Qualcomm
Snapdragon 865 - 83.54 mm²...
Let's say I make a hypothetical smartphone SoC called 'Flame 1' on the 7nm Node.
Then I introduce the 'Flame 2' SoC which is identical to the Flame1 in every way (same cpu, same gpu, same npu), except that it is built on the newer 7nm+ node.
Now let's say the 7nm+ Node give x% more...
The Offset voltage is changed to 0.1250V by BIOS of Ryzen. The cause of its bug and a mechanism were specified.
-Offset problem -
Basic : 0,0250V << Probably.
XFR: 0.0500V
TB: 0.0500V
Question) Why is Offset changed to 0.025+0.05+0,05 = 0.125V?
1) Vcore and 2) Base Offset 3) TB and 4) XFR...
Hello comunity,
I think all of you are familiar with intel’s tick tock strategy for CPU releases. I think we could identify a similar pattern with Apple SoC which became quite a topic over last few years. I see this as ticks being focused on energy efficiency and die size on even A chips...
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