1000 shader APU - when?

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Enigmoid

Platinum Member
Sep 27, 2012
2,907
31
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Enigmoid, Maxwell has twice the number of ROPs. It's not totally surprising that it has higher pixel throughput.

The consensus seems to be regardless of the ROPs, colour fill is bandwidth limited. 290/290X vs. 280X doesn't scale anywhere near 2x. Not sure what is happening with kepler there.
 

III-V

Senior member
Oct 12, 2014
678
1
41
You need both bandwidth, as well as ROP count. Nvidia manages such high fillrate because of superior color compression on GM204 compared to Hawaii (which doesn't have the significant compression improvements that Tonga does), which allowed them to double the ROPs while keeping them reasonably fed.
 

raghu78

Diamond Member
Aug 23, 2012
4,093
1,475
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Fixed it for you.

You didn't even post till I posted. Way to single me out raghu78.

somebody needs to fix this fixer. everybody know who is the butt of all jokes on ocn, semiaccurate, anandtech etc. Your posts are to put it aptly entertainment to some and pure trash to others :whiste:
 

NTMBK

Lifer
Nov 14, 2011
10,301
5,303
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Seronx- Basilisk was never openly confirmed, only appearing on a handful of LinkedIn profiles. For all we know it could be cancelled- and probably is, given that AMD are trying to get people to focus on K12 and Zen.
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,705
1,231
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Last edited:

NostaSeronx

Diamond Member
Sep 18, 2011
3,705
1,231
136
But what makes you think that's Excavator?
Any Bulldozer(15h) architecture after 2015 is obviously Excavator.
Also that Bhavani sounds rather like Carrizo's desktop variant :>


http://support.amd.com/Documents/kb/PEC-1 Files/MDDS_UOL721_(FS1B).pdf
http://www.heise.de/newsticker/meldung/AMD-Athlon-und-Sempron-kehren-wieder-2125393.html

FS1B = AM1
--
Carrizo 2015 -> Quad-core Excavator + 8 CU GCN IPv8
Basilisk 2016 -> Octo-core Excavator+ + 16 CU GCN IPvX
Zen 2016/2017 -> Quad-cluster Zen + 16? CU GCN IPvX

I do not expect a scenario like Broadwell and Skylake.
(If Basilisk follows Carrizo, December 2014 launch -> December 2015 launch, everything will be okay roadmap wise)
 
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NostaSeronx

Diamond Member
Sep 18, 2011
3,705
1,231
136
What's your source for Basilisk being 15h?
AMD

Bulldozer pre-2009 had four nodes(20nm/14nm counts as one) with accompanying APUs each.
45-nm SOI; CPU "Montreal" - Bulldozer // APU "Swift" - Stars // APU "Falcon" - Bulldozer
32-nm SOI; CPU "Sandtiger/Interlagos(Abu Dhabi)/Terramar" - Piledriver // APU "Llano" - Stars // APU "Trinity/Richland" - Piledriver

At this point is when the roadmap explodes.

28-nm SHP/22-nm SHP; CPU "Dublin/Boulder" - Steamroller // APU "Kaveri" - Steamroller
28-nm A/20-nm SHP/20-nm LPM; CPU "Austin" - Excavator // APU "Carrizo" - Excavator
14-nm Bulk/SOI FinFET; CPU "Gecko" - Excavator // APU "Basilisk" - Excavator

Underlined equals cancelled, and italics/bolds unconfirmed if being produced.

14nm FinFET Bulldozer is the last Bulldozer(15h) microarchitecture planned.

iGPUs
Swift/Falcon -> 160 ALUs + 40 SFU // Vec4+Scalar1
Llano -> 320 ALUs + 80 SFU // Vec4+Scalar1
Trinity/Richland -> 288 ALUs + 96 SFU // Vec3+Scalar1
Kaveri/Carrizo -> ~512 ALUs // Vec16
Basilisk -> ~1024 ALUs // Vec16

Regardless, end of 2015 to end of 2016 is the range for 1024+ ALU/Shaders.
 
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szatkus

Junior Member
Nov 17, 2014
16
0
66
Don't know how you did you get details about unreleased 45nm Bulldozer, but rest is wrong (even if you count units in iGPU).

K10: 3 ALUs per core
Bulldozer-family: 4 ALUs per module

It's not some kind of secret knowledge, there are a lot of documentation about AMD's cores.

Well, shame. I know about some AMD's design, but I don't know the name. Basilisk APU would fit, but I prefer some proof that Basilisk is Excavator.
 
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