Well, let round 16 of the video card wars begin.How can a $699 and $449 SKU crush Polaris?
You surely don't think those prices are affordable for the entry and mainstream masses.
In hardware terms, to crush something, you have to offer better performance at a similar price. If you only deliver marginally better performance at a higher price, you're competitive. Or vice versa, you deliver 90% of the performance at 25-40% less in price, you're very competitive.
AMD can't crush GP104, because they won't out-perform it. NV can't crush Polaris 10, cos they don't want to price their SKUs that low.
The battle is not on until GP106 is released for NV to have a chance vs Polaris 10. Likewise, until Vega, AMD has no chance to beat GP104.
Just like how massively OCing a 980Ti won't make it faster than a 390x when CF scaling works....
Had to highlight that part for you there. Not all games work well with crossfire and/or SLI. And to be perfectly honest, you are much less likely to have crossfire support on day one of a new game than you are to have SLI support. That said, as I mentioned both have problems which is why I typically just buy the fastest single GPU, which unfortunately hasn't been AMD for a while.
How can a $699 and $449 SKU crush Polaris?
You surely don't think those prices are affordable for the entry and mainstream masses.
In hardware terms, to crush something, you have to offer better performance at a similar price. If you only deliver marginally better performance at a higher price, you're competitive. Or vice versa, you deliver 90% of the performance at 25-40% less in price, you're very competitive.
AMD can't crush GP104, because they won't out-perform it. NV can't crush Polaris 10, cos they don't want to price their SKUs that low.
The battle is not on until GP106 is released for NV to have a chance vs Polaris 10. Likewise, until Vega, AMD has no chance to beat GP104.
Flexibility in arithmetic units is the enemy of power efficiency. I suspect this is why NVIDIA uses dedicated FP64 units in a market where area is less of a problem and power efficiency is way more important. There is nothing particularly hard or magical in fusing 2 or more ALUs to support wider operations.Yes and no.
AMD does FP64 very different to NV. They do not have dedicated ALU/CC that only runs FP64.
AMD's SP are very flexible, in that two SP can combine to process an FP64 workload or a single SP can process 2x FP16 (half-precision) workload.
I can't find any reference on FP16 ops running at double rate on GCN. Pointers? Even PS3 GPU, designed by NVIDIA, supports FP16 registers and some limited FP16 math, it's not exactly something new.This latter 2x FP16 ops has just been included in Pascal and hyped to the moon for "Deep Learning/AI" compute. You can chalk up one extra feature that Pascal is taking from GCN's books, along with instant graphics <-> compute switch, fine-grained preemption and 64x optimized wavefront.
I keep telling folks that GCN is old, but it aint obsolete and I hope they've started to realize that is the truth.
Flexibility in arithmetic units is the enemy of power efficiency. I suspect this is why NVIDIA uses dedicated FP64 units in a market where area is less of a problem and power efficiency is way more important.
.IIRC GP100 compute preemption is more fine grained than GCN's
Time to change hobby. I'm seriously considering it.
Area is not an issue in the HPC market, when they can sell a couple of chips for the price of the whole wafer why would they care about area as much as they do for the gaming market? Unused ALUs are clock gated, if not power gated.You must be joking. Cut down GP100 Tesla, 300W. Selling it for HPC that need FP64, all those FP32 are doing JACK ALL but eat up the chip space and TDP.
Same story.Selling it as a Quadro for rendering, all those FP64 CC are doing JACK ALL but eat up the chip space and TDP.
It is power efficient, not area efficient. If you are building a supercomputer with thousands of GPUs each costing thousands of dollars each, your power bill is still way higher than your GPU bill in the long term.Such an efficient design.
A well designed dedicated FP64 unit will use less power than 2 FP32 units fused together. Nothing groundbreaking here. The extra area, which is precious in the gaming market, is not a concern for HPC.It seems your bias has gotten the better of your processing capabilities to claim having separate 1:2 FP64 units is an efficient design.
If that's true, well done AMD. But I have my doubts There is much more to performance than peak flops In a modern GPU ALUs are probably less than 30% of the area of the chip. IIRC once AMD tripled their ALUs per pipe from one generation to the next and area hardly increased (don't ask me when/which product, it was a long time ago..)If NV could pull off what Hawaii does with 1:2 FP64, they would. A straight shrink & 2x of Hawaii to 14nm, ~400mm2, higher finfet clocks, and it would pwn P100 on FP64 performance. As a much smaller chip and less TDP.
Well, NVIDIA claims GP100 can preempt CUDA programs on per-instruction basis (page 9): https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdfRubbish.
If you're looking at AAA titles (maxed out settings no less) only, then by all means do so. Many decent, less demanding titles do exist, and they tend not to care what brand hardware you're running as long as it's decent. Some of my favorites will happily run on mediocre IGPs.Time to change hobby. I'm seriously considering it.
Well, NVIDIA claims GP100 can preempt CUDA programs on per-instruction basis (page 9): https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf
What's GCN pre-emption granularity in OpenCL?
The ACEs can switch between tasks queue, by stopping a task and selecting the next task from a different queue. For instance, if the currently running task graph is waiting for input from the graphics pipeline due to a dependency, the ACE could switch to a different task queue that is ready to be scheduled.
Yes and no.
AMD does FP64 very different to NV. They do not have dedicated ALU/CC that only runs FP64.
AMD's SP are very flexible, in that two SP can combine to process an FP64 workload or a single SP can process 2x FP16 (half-precision) workload.
NV is half way there. Volta will add the other half, but it'll need a hardware scheduler and a multi-engine design.
This is true, and Hawaii is a very space-efficient chip - probably the best perf/mm^2 of any of AMD's 28nm offerings. That said, there must be some tradeoff for that 1/2 FP64 support, since if adding that was "free" in terms of die space, why didn't they do it on Fiji?
Scheduling granularity *is not* the same thing as pre-emption granularity. The latter is about stopping processing, saving state and possibly re-load state and re-start at later time. Being able to schedule at wavefront/warp granularity has nothing to do with it. As far as I know GCN cannot stop executing a wavewront and give up its resources to another wavefront, until it has run to completion. When GCN is running compute and gfx on the same CU they are using distinct & separate resources. If you have a program executing a trillion iterations and you want to stop it and start doing something else you got to wait for it to complete first. If the program is stuck in an infinite loop, you are toasted. On Pascal a CUDA program can be interrupted at any time, at instruction granularity, and doesn't need to run to completion. Do you understand the difference now?Already had since GCN 1.0, even more granularity actually.
https://www.amd.com/Documents/GCN_Architecture_whitepaper.pdf
Here's what sebbi @ beyond3d had to say about Pascal's preemption:
https://forum.beyond3d.com/threads/nvidia-pascal-announcement.57763/page-32
Like I said, Pascal is taking some very nice features from GCN's books.
That's not peak utilization, you don't even cover ALU latencies with 2 warps, to not mention caches and memory latency.That 64x wavefront optimization is key for all console ports. The split to 32x2 each targeting 32x FP32 CC means Pascal hits peak utilization instantly like GCN does for game engines that use 64x wavefront.
Again, this is completely unrelated to what I was talking about (OpenCL, not graphics, pre-emption granularity, not scheduling granularity). We know nothing about GP104, all the information I quoted was from a GP100 white paper.Both GCN and Pascal can preemption and instant context switch graphics <-> compute. However, only GCN allows simultaneous graphics & compute workload to be processed by the CU/SIMDs, ie. wavefront granularity. True Async Shaders. NV is half way there. Volta will add the other half, but it'll need a hardware scheduler and a multi-engine design.
If you have a program executing a trillion iterations and you want to stop it and start doing something else you got to wait for it to complete first.
And extremetech conclusion :From Nvidia’s whitepaper:
Compute Preemption is another important new hardware and software feature added to GP100 that allows compute tasks to be preempted at instruction-level granularity, rather than thread block granularity as in prior Maxwell and Kepler GPU architectures. Compute Preemption prevents long-running applications from either monopolizing the system (preventing other applications from running) or timing out.
From what i read here it s like a limitation has been partialy removed but this is still below what is possible with GCN, in short, as pointed by Silverforce, Nvidia is just re inventing a GCN like wheel...This suggests that Pascal still won’t support asynchronous compute workloads in the same fashion AMD’s GCN hardware does, though the verdict is still out on whether this capability will play a significant role in shaping performance in a majority of DirectX 12 titles. It also suggests Pascal will see a smaller performance penalty with async compute enabled than Maxwell did, since it can interleave compute workloads more effectively than its predecessor.
A hardware scheduler probably burns more power than a software one, so it the performance gains from adding the necessary hardware/complexity to support "True Async" (something that developers seem to say adds 5-10% in performance) might not be worth the power consumption trade-off (i.e. there could be other ways to get that performance increase elsewhere that, for NV, may be more efficient) in a particular generation/at a given node.
The architects at both AMD and NVIDIA are very smart and I'm sure there's good reasoning behind the trade-offs that both IHVs make.
@Abwx
Async Compute is as much a factor as GPU PhysX (ie. not much), because DX12 games don't auto use it unless AMD sponsors and add it.
Pascal has just what it needs to perform well in a future where games use more compute effects, and importantly, for VR.
Why? Computer gear is awesome
http://www.extremetech.com/extreme/...axwell-production-ahead-of-june-pascal-launch
And extremetech conclusion :
From what i read here it s like a limitation has been partialy removed but this is still below what is possible with GCN, in short, as pointed by Silverforce, Nvidia is just re inventing a GCN like wheel...
Wait til you guys see the reviews based on the Nvidia reviewer guide!
It would be nice if people would actually read and understand what they read before replying with the usual async compute story. Let me explain it again: async compute and scheduling granularity have *nothing* to do with preemption granularity. You can have a great architecture that can schedule compute and gfx work on the same SIMD processor at the speed of light and run it concurrently and you might still have to wait 3 seconds (or forever ) for a warp/wavefront to run to completion and free its resources (registers, etc.).
On GP100 CUDA programs can be interrupted at any time, you just need to wait for an instruction to be completed. No more driver timing out because the program doesn't stop, no more waiting milliseconds to get control of the GPU (again, in CUDA). This has nothing to do with async compute, so please, just stop bringing it up. Thank you
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Compute Preemption is another important new hardware and software feature added to GP100 that allows compute tasks to be preempted at instruction-level granularity, rather than thread block granularity as in prior Maxwell and Kepler GPU architectures. Compute Preemption prevents long-running applications from either monopolizing the system (preventing other applications from running) or timing out. Programmers no longer need to modify their long-running applications to play nicely with other GPU applications. With Compute Preemption in GP100, applications can run as long as needed to process large datasets or wait for various conditions to occur, while scheduled alongside other tasks. For example, both interactive graphics tasks and interactive debuggers can run in concert with long-running compute tasks.
so how do you explain nvidia's own whitepaper? are they lying? it was some sort of typo's?Flexibility in arithmetic units is the enemy of power efficiency. I suspect this is why NVIDIA uses dedicated FP64 units in a market where area is less of a problem and power efficiency is way more important. There is nothing particularly hard or magical in fusing 2 or more ALUs to support wider operations.
I can't find any reference on FP16 ops running at double rate on GCN. Pointers? Even PS3 GPU, designed by NVIDIA, supports FP16 registers and some limited FP16 math, it's not exactly something new.
The rest is inaccurate or just wrong. IIRC GP100 compute preemption is more fine grained than GCN's. Also GP100 doesn't have 64 wide warps, which are still 32 wide. They simply split their SM in two halves doubling the register file for each half. Both physical and logical warp sizes are unchanged, so no, they didn't go the GCN route, apart from putting down more registers, which is something NVIDIA has been doing pretty much any generation.
GCN is a *great* architecture but to suggest NVIDIA is copying it or imitating it is based on wishful thinking. Do you really think that developer computing architectures work that way? Let's be serious.