16nm node for semiconductor lithography is the end of Moore's law

[hellokeith]

IBM, Intel, and Toshiba are already talking about 22nm node. So I looked around about how these node shrinkages are achieved.

Basically, the lithography people are saying that 16nm is the last node, because the gates which control the electron flow will be 6-10nm. Once you get to a gate thickness of 5nm, electrons start quantum tunneling through the gate, thus making it impossible to reliably have a gate. Thus, lithography is at an end.

One researcher said that we could continue Moore's law while staying at 16nm for several generations by just making larger (length x width) chips, though obviously there are eventual limits to this as well (size of the chip, energy required).

Anybody work in this area? Have any thoughts?

 

[TuxDave]

A brief look at history you'll see people always saying that Moore's law is coming to and end. The fact that it MUST end at some point is pretty obvious but the "when" is always up to debate. People said once you drop to sub-micron tech (below 1um or 1000nm) gates that we'd be broken yet here we are working with 45nm chips. So Moore himself put it best by saying that all exponential laws cannot go on forever, but we can delay forever.

On a more relevant point, quantum tunneling has been occurs even at today's technology node. We found a solution with our high-k dielectric to increase the gate oxide thickness to allow us to continue shrinking and pushing out the date for when quantum tunneling just shorts power and ground.

The other point factor coming into play is the variation of our transistor. We're coming to a point where we can start counting the number of atoms in the transistor and so adding or removing ONE DOPANT ATOM will start having significant effects on chip timing. We can try to push this out by perhaps changing how we design chips. Having a CMOS gate go anywhere from 1x to 100x the speed we expect is going to make a design impossible (given today's methodology)

 

[firewolfsm]

I was actually wondering if it would interfere. I guess I was right about that.

I'd say the next comes from using that to our advantage.

 

[esun]

What you've read is generally the consensus. Somewhere around the 10 nm node, we will have to move away from the traditional MOSFET structure to something else. What this will be remains to be seen. Multi-gate/FinFET devices is a strong candidate to replace the traditional Si MOSFET within the next few years, but implementing these technologies into large-scale production is much more difficult than making them in a research lab. Beyond that, there have been ideas with nanotube transistors, graphene transistors, and others that could be used (though none of them are ideal in terms of the features that Si MOSFETs provide currently).

As TuxDave said, modern MOSFETs already have to deal with leakage as a result of quantum tunneling, which is one reason why Intel went to a high-K dielectric and metal gate at the 45 nm node.

If you're really interested in the details, the ITRS is a good guide for what people are thinking in terms of both short-term and long-term goals for semiconductors. http://www.itrs.net/Links/2007ITRS/Home2007.htm has a lots of very interesting information about what devices are candidates for replacing the traditional Si MOSFET. The Executive Summary has a lot of useful information if you don't want to read all of the individual sections.

 

[BrownTown]

Originally posted by: esun
What you've read is generally the consensus.

The thing is that it been the general consensus for decades, basically they always say that the node 2-3 out is physically impossible, but they always make it. The statement that we will have to change the structure alot is true, but its already happened many times over the years. Just look at 45nm high-k, its waaay different then what came before it, not jsut in the structure, but in the way it is fabricated.

I remember when they were saying 45nm was more or less gonna be impossible, it wasn't more than a few years ago even.

 

[esun]

I disagree. The 45nm node is not all that different from previous technologies, even with high-k and metal gates. Intel basically builds a normal MOSFET, etches out the poly gate, and replaces it with a metal gate. Obviously a lot of work went into choosing the specific process flow and materials, but the overall structure and process is very similar to what they've been using all along, aside from that last step.

Moving to around 10nm, we'll likely see a much larger structural change. A 10nm channel length means there are about 20 Si atoms across the surface of the channel. As TuxDave mentioned, that's a huge issue, because the variation due to a single dopant atom becomes a huge problem.

I don't think lithographic processing will end (perhaps I shouldn't have been so hasty to agree with the OP generally when his statement was specific). But the structure is not going to be a planar MOSFET like they're using now.

 

[citan x]

I don't think lithography is connected with electron tunneling in the gates of a transistor. To my understanding, lithography is a way to make integrated circuits, and the tunneling of electrons disturbs how transistors work. Nevertheless, there are challenges to be solved with both lithography and electron tunneling as ICs get smaller and smaller.

 

[TuxDave]

Originally posted by: citan x
I don't think lithography is connected with electron tunneling in the gates of a transistor. To my understanding, lithography is a way to make integrated circuits, and the tunneling of electrons disturbs how transistors work. Nevertheless, there are challenges to be solved with both lithography and electron tunneling as ICs get smaller and smaller.

 

[BrownTown]

Originally posted by: citan x
I don't think lithography is connected with electron tunneling in the gates of a transistor. To my understanding, lithography is a way to make integrated circuits, and the tunneling of electrons disturbs how transistors work. Nevertheless, there are challenges to be solved with both lithography and electron tunneling as ICs get smaller and smaller.

you do realize that some people here actually have degrees in this subject,s o not everyone is talking out their ass here...

 

[f95toli]

Originally posted by: BrownTown
I remember when they were saying 45nm was more or less gonna be impossible, it wasn't more than a few years ago even.

Well, in a way they were right; it is nearly impossible which is why the technology it is so extremely expensive. A few years ago I listened to a good talk about the future of microelectronics and I remember the speaker was pretty pesimistic; the reason being the economic barriers. The example he used was the cost to fabricate a mask which even back then (this must have been in 2002 or so) was so high that few companies could actually afford to them, and the masks is of course just a minor part.
Today we have a situation where only a handfull of companies can afford to use the most recent technologies and many of them are struggling (AMD being a good example), most electronics is made using "old" processes.
Another sign of this change is of course the move to several cores as an alternative to making faster CPUs, I might be wrong but I don't think the clock frequencies have gone up much over the past 2-3 years.

My point is that we have already come across quite a few problems that we can't seem to solve despite an enormous amount of money being spent on R&D (e.g. the rising costs, methods like self-assemby etc are still nowhere near ready for use production).
In most cases we don't notice these because Intel&Co have come up with several clever "workarounds" and are still selling so many CPUs that they can afford to build new fabs; although I am starting to wonder how long they will be able to keep this up.

I am pretty sure we are nowhere near the "physical limit" (remember that even 45nm transitors are pretty big compared to some of the things that are routinely made in research labs using modern nanolithography, but then we are of cause usually only dealing with single devices).
I am sure we will see smaller transitors; but making devices using direct-write E-beam lithography is one thing; mass production another.

 

[hellokeith]

Here's a pretty good presentation from Intel on the 40 years (1967-2007) of silicon IC development and 2008 research for future node shrinkages: Silicon - Yesterday, Today, Tomorrow, and After

Quantum mechanical/thermal/electromagnetic effects are a big concern to the litho people, and the Intel researcher in that presentation says essentially the same thing, that CMOS will not be able to keep pace with Moore's law.

 

[frostedflakes]

Originally posted by: BrownTown

Originally posted by: esun
What you've read is generally the consensus.

The thing is that it been the general consensus for decades, basically they always say that the node 2-3 out is physically impossible, but they always make it. The statement that we will have to change the structure alot is true, but its already happened many times over the years. Just look at 45nm high-k, its waaay different then what came before it, not jsut in the structure, but in the way it is fabricated.

I remember when they were saying 45nm was more or less gonna be impossible, it wasn't more than a few years ago even.

As I understand it, there is definitely a physical limit for silicon transistors. We're getting to the point where gates are only a handful of atoms thick. How do you keep shrinking after gate thickness reaches one atom? There may be some clever engineering that can keep leakage current in control using such small gates, but reducing the size of the silicon atoms is probably beyond our capabilities.

 

[Cogman]

as far back as I can remember there has been "problems" with going smaller. At one time people said there would be no way for use to have processors with over 200 MHZ clock speeds. (though, to be honest, 3.0-4.0 GHZ is starting to look like our maximum frequency).

Eventually, we won't be able to shrink our processors any more, and that day is coming sooner then later. The fact of the matter is, we are nearing the point where gates are only 10-20 gates thick.. What do we do when they are 1-2 atoms thick (if thats even possible), start using quarks?

Im not saying they won't find a direction to go to get high speeds, but I do think the direction soon will not be smaller nodes, but instead different methodologies. Perhaps more specialize parts like the ALU. but instead you have a part of your cpu dedicated to MP3 decoding, and another dedicated for OS operations. ect.

 

[firewolfsm]

Once research in node tech winds down, we'll see more money pumped into specialization, processors for graphics, physics and music are already here, we'll have more and more as time goes on, eventually all on the same package or die, sharing components and cache. We also have 3D, multilayer processors to develop, I think a cube could offer the highest interconnect bandwidth between transistors and increase surface area. Then there's photon transfer for communication. Graphene rather than silicon, it should be able to scale to smaller sizes. We also have carbon based, organic computing which is starting to show some promise. There are some studies using macro-molocules to hold information through the shape of the molocule itself, it seems to work at hexagonal scales rather than just binary. We also have quantum computing to figure out.

There's A LOT to keep us busy for the next 50 years. After that, I'm sure we'll have come up with more.

I've never taken a class on nano-architecture but I think if we had non-specific transistors in a pool of sorts, that could be reprogrammed and arranged through hardware or software we could have more efficient processors.

 

[soccerballtux]

Yes definitely rough times ahead. Like dmcowen, I forecasted this years ago.
3d silicon will likely be the future for a bit, just need to find ways to cool it.

 

[bobsmith1492]

Originally posted by: firewolfsm


I've never taken a class on nano-architecture but I think if we had non-specific transistors in a pool of sorts, that could be reprogrammed and arranged through hardware or software we could have more efficient processors.

Look up FPGA and ASIC... they've been around for a while.

 

[krotchy]

Originally posted by: bobsmith1492

Originally posted by: firewolfsm


I've never taken a class on nano-architecture but I think if we had non-specific transistors in a pool of sorts, that could be reprogrammed and arranged through hardware or software we could have more efficient processors.

Look up FPGA and ASIC... they've been around for a while.

Did you mean FPGA and CPLD? A typical ASIC might be modeled using an FPGA, but when it goes into production its not a "pool" anymore like a CPLD or FPGA.

 

[firewolfsm]

That always happens! I come up with an idea, then find out it's already been done, and to lesser success than I thought possible, haha.

 

[BladeVenom]

Once you go 3d and have a million layers, that should keep Moore's law going a little while longer.

 

[faxon]

Originally posted by: BladeVenom
Once you go 3d and have a million layers, that should keep Moore's law going a little while longer.

good luck cooling it though!

 

[williama]

Cooling? Use the water tech that IBM's perfecting


http://www.redorbit.com/news/t...ips_cooled_with_water/

 

[citan x]

Originally posted by: BrownTown

Originally posted by: citan x
I don't think lithography is connected with electron tunneling in the gates of a transistor. To my understanding, lithography is a way to make integrated circuits, and the tunneling of electrons disturbs how transistors work. Nevertheless, there are challenges to be solved with both lithography and electron tunneling as ICs get smaller and smaller.

you do realize that some people here actually have degrees in this subject,s o not everyone is talking out their ass here...

I have a degree and I talk out of my ass all the time. Anyways, I still don't see the direct relationship between tunneling and photolithography. (I am assuming the op was referring to photolithography when he mentioned lithography.) Maybe someone can explain it to me. I do hate it when I can't see the obvious. (And that happens much more often than I like.)

 

[Gibsons]

Okay, dumb, naive question: what's the wavelength of an electron in a cpu environment?

 

[RichUK]

Originally posted by: Gibsons
Okay, dumb, naive question: what's the wavelength of an electron in a cpu environment?

0.82nm

 

[BEL6772]

Originally posted by: citan x

Originally posted by: BrownTown

Originally posted by: citan x
I don't think lithography is connected with electron tunneling in the gates of a transistor. To my understanding, lithography is a way to make integrated circuits, and the tunneling of electrons disturbs how transistors work. Nevertheless, there are challenges to be solved with both lithography and electron tunneling as ICs get smaller and smaller.

you do realize that some people here actually have degrees in this subject,s o not everyone is talking out their ass here...

I have a degree and I talk out of my ass all the time. Anyways, I still don't see the direct relationship between tunneling and photolithography. (I am assuming the op was referring to photolithography when he mentioned lithography.) Maybe someone can explain it to me. I do hate it when I can't see the obvious. (And that happens much more often than I like.)

So yeah, the OP convolved issues. He said that lithography wouldn't work past the 16nm node due to quantum tunneling. If you take that literally, it is false.

The steppers, lasers, masks, lenses, and photoresist used in litho tools could care less about quantum tunneling. Their issue is how to get a reliable ~6nm feature printed using 193nm wavelength light (or even with electron-beam lithography, for that matter).

Assuming litho tech advances to that point, then there is the issue of quantum tunneling in the resulting devices. The tunneling issue would make todays planar CMOS transistors useless at those gate sizes.

So there is no clear path to getting beyond the 16nm node. Everybody knows that. I think that the OP just used the word 'lithography' to represent our current process and resulting planar CMOS transistor rather than to represent the actual process of using light to pattern a wafer.