64 core EPYC Rome （Zen2）Architecture Overview？

[kokhua]

That may be short on eye sight but electrically that s extremely long, 2-3mm amount to a 1/4 wave length at 30GHz and 1/2 wave length at 60GHz, that s largely within the spectrum range of a 3GHz clock square signal, meaning that such a wire is incapable to transmit the higher harmonics of the signal wich are the frequency elements that make the slope of the rising and falling hedge being abrupt.

I wont even talk of a 60Gbit SerDes since the signal wouldnt even appear at the terminal of the receiver, as all energy would be diffused by the conductors wich would act as a perfectly tuned antenna..

Think DDR4/5 like signalling but at much shorter trace lengths.

 

[DisEnchantment]

Apparently AMD made some investigations in this area.

[0023] The semiconductor chips 20, 25 and 30 may be any of a myriad of different types of circuit devices used in electronics, such as, for example, microprocessors, graphics processors, combined microprocessor/graphics processors, application specific integrated circuits, memory devices, active optical devices, such as lasers, passive optical devices or the like, interposers, and may be single or multi-core or even stacked laterally with additional dice.

http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20180102338".PGNR.&OS=DN/20180102338&RS=DN/20180102338

 

[DrMrLordX]

8c/16t with 8 channel DDR4? Sign me up please.

 

[kokhua]

8c/16t with 8 channel DDR4? Sign me up please.

No need to wait for Rome. It’s already available: https://www.amd.com/en/products/cpu/amd-epyc-7261

 

[Atari2600]

I don't understand what you mean by "L4 cache is a duplicate of all L3 cache".

Simply that anything within L3 is also duplicated in L4. Thus, if two CCX requires the same data, two requests to system memory are not required and the two L3 are not populated in separate operations. Later requests for the same data by other CCX could then be serviced from L4 directly, i.e.:
(1) CCX1 -> MC -> L4 -> CCX1
rather than CCX1 -> MC -> L3 CCX2 -> MC -> CCX1

That obviously does not mean L4 would contain exclusively data that is elsewhere within L3.

 

[DrMrLordX]

No need to wait for Rome. It’s already available: https://www.amd.com/en/products/cpu/amd-epyc-7261

Not overclockable though . . . and let's face it, Rome won't be either.

But if Rome has a 8c/16t 8-channel option, there's a possibility that Zen2 or Zen3 desktop chips may provide the same thing. If AMD is crazy enough . . .

hell I'd settle for quad channel memory being standard on ATX boards with 4 DIMM configurations. AMD will need it for anything beyond 8c anyway.

 

[Glo.]

https://www.semiaccurate.com/2018/10/29/more-details-about-amds-rome-cpu-leak/

Where are those saying there will be 12 Core AM4 platform, max?

Its single 8 core cluster.

 

[tamz_msc]

https://www.semiaccurate.com/2018/10/29/more-details-about-amds-rome-cpu-leak/

Where are those saying there will be 12 Core AM4 platform, max?

Its single 8 core cluster.

Is Rome still going to be 8+1 or something else? That blurb before the paywall isn't clear enough on this matter.

 

[Glo.]

Is Rome still going to be 8+1 or something else? That blurb before the paywall isn't clear enough on this matter.

Yes, it will be 8+1.

 

[darkswordsman17]

Whether AMD will win supply deals is only partly based on the quality of product they can supply - the same applies to Intel.
Sales are dependant on finance options, personal politics, marketing campaigns, added value products, pre-existing tie-in deals, associated products, and plain ol'branding and lies - not "tech" lies, just lies.
Consider that they actually sold a great deal of Bulldozer chips, when no (non-partisan) enthusiast would buy one. Why ?
Because they got sales people who know the art of selling.
They could sell sand to an arab; a fridge to an eskimo.
The quality of the product is *not* the primary decision factor.

Again, how is that a response to my post...in any meaningful way? Where did I say anything about quality or act like that had anything to do with any aspect of what I was talking about? You're just spouting generic "sales" nonsense that in no way addresses any point I made. Frankly it doesn't address any discussion in this thread and you could post it in literally every thread in this forum and it'd make as much sense (which is to say not much).

And sorry, but that's complete garbage argument. If AMD's sales people were so amazing, why were they on the verge of going out of business for years? Why did they have to rack up tons of debt just to eke by? Why were they constantly rumored to be bought by other companies? AMD sold Bulldozer because they priced it where it could sell (which was very low) and while it wasn't great its not like it was outright broken. The APUs especially were alright mostly thanks to the GPU (but most importantly were cheap).

What a weird argument. "Quality doesn't matter, that's why Bulldozer was a failure that almost put AMD out of business, that got trounced in enterprise and also consumer until AMD dropped the prices so low they barely made any money." Great logic...

 

[DigDog]

Simply that whether or not AMD can land the Apple supply deals is yet to be seen, because there are many factors that could affect that decision.

It wasnt terribly hard to understand even the first time around, non?

 

[DownTheSky]

Seems like 8+1 config is pretty much confirmed.

 

[Vattila]

Yeah. AdoredTV corroborates the optimistic rumours about EPYC 2 in his latest video. A lot of juicy stuff in this one:

• 8+1 chiplet design confirmed,
• 32 MB L3 per 8-core chiplet (256 MB total for 64-core),
  
• details on Zen 2 bring-up and performance ("extreme" 2-core turbo),
• discussion on TSMC's 7nm HPC process,
• expects 2019-Q1 launch with hyper-scalers, 2019-H2 for OEM system availability,
  
• rumour that some OEMs are deserting Intel's lacklustre roadmap until 2021, and
• hinting about something mysterious called "ZenX".

Except for the L3 size, he has no new information about how the chiplets are architected, though.

 

[Vattila]

"According to Ashraf Eassa AMD confirmed to him that Zen2 + Vega20 will use 7nm HPC. The 7nm numbers you used as a reference are from 7nm mobile [with 6T cells] which is a lot denser (>90MTr/mm²). Zen1 uses 14nm LPP HD with 9T cells (33MTr/mm²). Zen2 uses 7nm HPC with 7.5T cells (67MTr/mm²)."

https://twitter.com/Locuza_/status/1057184301152792577

 

[lixlax]

If this all is true then where does it leave consumer/AM4? I see it being almost impossible to fit such a chiplet design in AM4 form factor or are they going to design a separate standard monolithic die for consumer market with all the IO attached? If it is a similar chiplet design then we'll see 1+1 and 2+1 variants (8 and 16 core)?

Those tiny 8c chips should have nice yields as well compared to anything larger.

Edit: If the server chips are really as good as rumored then I can't see 7nm Ryzen chips any time soon because all the capacity will be used to produce Epyc's (thats ofcourse if they gain popularity/market share). Maybe q3-q4 for Ryzen?

 

[Atari2600]

If this all is true then where does it leave consumer/AM4? I see it being almost impossible to fit such a chiplet design in AM4 form factor or are they going to design a separate standard monolithic die for consumer market with all the IO attached? If it is a similar chiplet design then we'll see 1+1 and 2+1 variants (8 and 16 core)?

Would they not just have a common 8 core "core", then various different designs of uncore depending on their target.

So, along the lines of:
DT#1: 1C + UC1a [1x 8core CCX + Uncore which interfaces 1 CCX to the wider system - 2 ChDDR4]
DT#2: 2C + UC1a [2x 8core CCX + Uncore which interfaces 2 CCX to the wider system - 2 ChDDR4]
HEDT#1: 2C + UC2b [2x 8core CCX + Uncore which interfaces 2 CCX to the wider system - 4 ChDDR4]
HEDT#2: 3C + UC3b [3x 8core CCX + Uncore which interfaces 3 CCX to the wider system - 4 ChDDR4]
HEDT#3: 4C + UC4b [4x 8core CCX + Uncore which interfaces 4 CCX to the wider system - 4 ChDDR4]
PROF#1: 2C + UC2c [2x 8core CCX + Uncore which interfaces 2 CCX to the wider system - 8 ChDDR4]
PROF#2: 4C + UC2c [4x 8core CCX + Uncore which interfaces 4 CCX to the wider system - 8 ChDDR4]
PROF#8: 8C + UC2c [8x 8core CCX + Uncore which interfaces 8 CCX to the wider system - 8 ChDDR4]

Yes, that does mean many different design of system controller, but they could look for commonality there.
- Common memory channels, then there can be CCX interfaces fused off.
- Common CCX, with additional memory channels activating depending on bios switches [this would be really impressive - if technically very challenging - lower the cost of entry to HEDT and lower cost of server build - if you don't need the bandwidth].
- One Uncore to rule them all - combination of both of above. Most technically challenging, but would allow for superb flexibility both in product and in how user can build on the initial installation of the product.

 

[Vattila]

If the server chips are really as good as rumored then I can't see 7nm Ryzen chips any time soon because all the capacity will be used to produce Epyc's (thats ofcourse if they gain popularity/market share). Maybe q3-q4 for Ryzen?

AMD CEO Lisa Su has stated on several occasions that fab capacity is not a limiting issue. Her projections for 10% (or "double-digit") server market share by end of 2019 is based on customer adoption rate (dependent on validation time, etc.), and that TSMC is very supportive of their roadmap and needs. See the latest Q3 earnings call transcript.

Would they not just have a common 8 core "core", then various different designs of uncore depending on their target.

It all comes down to packaging technology, I guess. If they have the packaging capacity and low cost needed for mainstream, they may do a chiplet/MCM approach for Ryzen, reusing the same 8-core CPU chiplet they are using for EPYC 2. Otherwise, I guess Ryzen 3000 will be a separate 7nm 8-core APU, targeting both mainstream desktop and high-end notebook.

 

[Glo.]

What do you guys think about possibility that AM4 products will end up on 16C/32T CPU, and start with 8C/8T Ryzen 3, one?

I will quote myself.

So. What do you guys think about this possibility?

Ryzen 3 3200 - 8C/8T
Ryzen 5 3400 - 8C/16T
Ryzen 5 3600 - 12C/24T
Ryzen 7 3700 - 16C/32T

SKUs will cost the same as currently. 8C/8T for 109$? 8C/16T - 169$?

AMD will want to MURDER everything that is on the market. Both server, and mainstream consumer platforms.

 

[inf64]

I will quote myself.

So. What do you guys think about this possibility?

Ryzen 3 3200 - 8C/8T
Ryzen 5 3400 - 8C/16T
Ryzen 5 3600 - 12C/24T
Ryzen 7 3700 - 16C/32T

SKUs will cost the same as currently. 8C/8T for 109$? 8C/16T - 169$?

AMD will want to MURDER everything that is on the market. Both server, and mainstream consumer platforms.

I think that your proposed lineup is not only possible but very likely to happen. 2 x 7nm chiplets for mainstream DT segment will be the new performance standard.

 

[Vattila]

One Uncore to rule them all

Yeah. Regarding HEDT, I doubt AMD will design dedicated dies. The segment is currently too small for that. Remember, Threadripper was an unplanned skunkworks project in the first place. So, I think everything they do here will reuse the server platform, perhaps just by using fewer CPU chiplets and fusing off things on the System Controller die.

What do you guys think about this possibility? [8C to 16C Ryzen]

If they have the low-cost packaging to enable an MCM approach in the mainstream, they could go beyond 8 cores. But I don't think there is much demand or need to do so, and with dual-channel memory, 8-core is the sweet spot, I guess. A monolithic 8C/16T APU with CPU performance beating Skylake should be more than competitive in the mainstream until Zen 3.

 

[JoeRambo]

Flat 8C chip with 32MB of performant L3 is a dream setup for AMD. Even if they bolted current Ryzen core to this massively improved uncore, perf would go way up. Each core having access to 32MB instead of 8MB would work wonders for quite a few workloads including gaming.

 

[Glo.]

DRAM prices falling, SSD prices falling, CPU market is going to have a massive earthquake. AMD Navi will be released. 2019 appears to be best year for computer enthusiasts in a very long time.

 

[LightningZ71]

I suspect that there will be three different TSMC chips produced, a thin 8 core chiplet for Epyc/Threadripper, a versatile I/O chiplet for Epyc/Threadripper, and a fat 8 core chip for desktop that will have all the needed I/O to work with AM4. They will retain the APUs at GF, moving to the 12nm node, maybe with optimized libraries for the next iteration. I suspect that the thin chiplets will have the larger L3 (32MB) and hardly any I/O, save for the high speed parallel data connection to the I/O chip. The desktop chips will likely still have 16mb of L3, but may gain a tiny iGPU in the 3CU range. I suspect that qualified DDR-4 speeds will be in the 3200-3400 range. I don't see the extra packaging costs of an MCM for the AM4 platform making up for the cost of an extra die that is only somewhat larger than the chiplet one to accommodate the I/O. I also think that the MCM will negatively affect the total package height, causing coolers for existing AM4 processors not to work properly on the Ryzen 3 generation. This goes out the window is they have a new interposer technique that they plan on using. I don't expect a 7nm APU until 2020 at the earliest, and that would only be on a mature 7nm process optimized for efficiency/density as opposed to performance.

 

[SPBHM]

DRAM prices falling, SSD prices falling, CPU market is going to have a massive earthquake. AMD Navi will be released. 2019 appears to be best year for computer enthusiasts in a very long time.

is AMD releasing a 7nm AM4 CPU with more than 8 Cores? it looks like their dies are all 8 cores still, so I wouldn't expect a huge change for desktop CPUs at least...


the Epyc with twice the dies and the controller chip is looking very interesting, I wonder if it's just a controller or if there is another l4 cache in there?!

 

[Tuna-Fish]

a thin 8 core chiplet for Epyc/Threadripper ... and a fat 8 core chip for desktop that will have all the needed I/O to work with AM4

I see very little chance that this will happen.

One of the big reasons AMD wants to architect it's product lines like they are doing them is that the cost of mask sets per chip has more than doubled every new process node. On 14nm, they touted only having 2 distinct chips and serving the entire market from APUs to massive servers with them as a major win. Now, they have had to pay even more for a single design. My bet is that if they truly are going with a small, 8-core chiplet with a separate IO die, it's because they intend to serve their entire product line, from laptops through desktops to servers with it. That is, an "APU" would just have a different kind of IO chip with a GPU in it.