So when you have all four slots filled, does that mean that the two sets of dual-channel RAM are communicating with the CPU through the same pins?
If you are asking if there are currently > 280 unused pins in AM4 package required for the two additional memory channels, the answer is no.
So when you have all four slots filled, does that mean that the two sets of dual-channel RAM are communicating with the CPU through the same pins?
Not certainly. If the controller chip is built to be modular they could make a smaller one specifically for AM4 quite easily. That saves them from another 7nm tape out as the controller is 16nm/14nm.If AMD goes with chiplets, they will certainly have a different dies for server and desktop, so everything discussed here (rome rumours) could have zero impact on the AM4 platform.
So when you have all four slots filled, does that mean that the two sets of dual-channel RAM are communicating with the CPU through the same pins?
Yes. This is why going from single channel to dual channel doubles bandwidth, but putting two sticks of RAM into the same channel doesn't. The two sticks on the same channel are attached to the same bus, and the memory controller can only talk to one of them at a time.
So when you have all four slots filled, does that mean that the two sets of dual-channel RAM are communicating with the CPU through the same pins?
Quad channel capability on AM4 would require 286 additional pins to be available (143 per channel), increasing the total pin count reserved for the memory interface from the current 286 to 572 (i.e. to 43% of the total pin count of the package).
I am no engineer and It's 20 years plus back I was working with reducing jitter in audio signals for fun. Filtering function in pll. Decoupling, reference clock what not. Dip times. It was beneficial for the jitter results to simply view the ground as part of the signal path. And why not.And effectively more than that, because the high-speed transmission pins need ground pins next to them to maintain signal quality.
That will make them develop specific IO dies only, on cheap as f*** 14 nm process. Which will in return turn into more profit, and saving moneyz on manufacturing.Not certainly. If the controller chip is built to be modular they could make a smaller one specifically for AM4 quite easily. That saves them from another 7nm tape out as the controller is 16nm/14nm.
So server and client would share cores, but the controller/IO die would be specifically per segment.
The saving a tape out part is only true, if they won't make a 8 core raven ridge succesor (that would easily work, even on mobile). If they do, thry might opt out from 12-16 core AM4 multichip parts. They could of course also do bothNot certainly. If the controller chip is built to be modular they could make a smaller one specifically for AM4 quite easily. That saves them from another 7nm tape out as the controller is 16nm/14nm.
So server and client would share cores, but the controller/IO die would be specifically per segment.
That will make them develop specific IO dies only, on cheap as f*** 14 nm process. Which will in return turn into more profit, and saving moneyz on manufacturing.
That will make them develop specific IO dies only, on cheap as f*** 14 nm process. Which will in return turn into more profit, and saving moneyz on manufacturing.
The circuit structures of the chiplets 50 and 55 may be constructed using one more design rules for higher density circuit structures while the circuit structures of the remainder of the circuit board...
The chiplets 50 and 55 may be used for a variety of purposes. For example, the chiplet 50 may be used to provide large numbers of electrical pathways between the semiconductor chip 20 and 25 as well as electrical pathways to and from the semiconductor chips 20 and 25, through the circuit board 15 and out to the I/O's 45 if desired. The chiplet 55 may be used to provide large numbers of electrical pathways between the semiconductor chip 25 and the semiconductor chip 30 as well as electrical pathways to and from the semiconductor chips 25 and 30 through the circuit board 15 and out to the I/O's 45 if desired.
[0020] Referring to FIG. 1, processing system 100 (e.g., a server) includes multiple processing nodes (e.g., node 0 and node 1). Each processing node includes multiple caching agents (e.g., processors 102 and 104 coupled to main memory 110). For example, caching agent 102, is a processor including core 0, core 1, core 2, . . . core 7 and caching agent 104, is a processor including core 0, core 1, core 2, . . . core 7) and a memory system. Each of the nodes accesses its own memory within corresponding coherence domain 122 faster than memory in non-coherence domain 124 (e.g., main memory 110) or memory in another node. As referred to herein, a coherence domain refers to a subset of memory (e.g., cache memory of node 0) for which a cache coherence mechanism maintains a coherent view of copies of shared data. A non-coherence domain refers to memory not included in the coherence domain (e.g., main memory 110 or cache memory in another node). Each of the caching agents in a node includes a last-level cache shared by the cores of the caching agent. Each core includes a private penultimate-level cache. For example, caching agent 102 includes last-level cache 128, which is a level-three cache shared by core 0, core 1, core 2, . . . core 7, and includes a level-two cache within each of core 0, core 1, core 2, . . . core 7. Last-level cache 128 and each level-two cache of caching agent 102 includes storage elements, e.g., storage implemented in fast static Random Access Memory (RAM) or other suitable storage elements. Cache control logic is distributed across last-level cache 128 and each level-two cache of caching agent 102. The caching agents use inter-processor communication via directory controller 121 to maintain coherency of a memory image in main memory 110 when caches of more than one caching agent contain the same cache line (i.e., a copy of contents of the same location of main memory 110) of coherence domain 122. In at least one embodiment of processing system 100, probe filter 112 includes storage for a cache directory used to implement a directory-based cache coherency policy. Probe filter 112 is implemented in fast static RAM associated with directory controller 121 or by other suitable storage technique.
[0019] Processing system 100 includes a distributed, shared memory system. For example, all memory locations of memory system 108 are accessible by each of processors 102, 104, and 106. Memory system 108 includes multiple memory portions, which are distributed across processors 102, 104, and 106. Memory portion 110 is local to processor 102 (e.g., tightly integrated with processor 102) and remote to processors 104 and 106 (e.g., within processing system 100 and accessible to processors 104 and 106, but not local to processors 104 and 106).
APU in this design can also be chiplet based.The saving a tape out part is only true, if they won't make a 8 core raven ridge succesor (that would easily work, even on mobile). If they do, thry might opt out from 12-16 core AM4 multichip parts. They could of course also do both
Not certainly. If the controller chip is built to be modular they could make a smaller one specifically for AM4 quite easily. That saves them from another 7nm tape out as the controller is 16nm/14nm.
I would imagine there's also a power and performance price to be paid. That price is easily offset on a many-CCX platform like EPYC or TR, but not on mainstream.Add the more complex packaging (price, yields, size, ...) to it and IMO it makes less and less sense to go chiplets for desktop usage.
We need someone to put some numbers to the table here. Can someone do that?Yes, 14/16nm is cheaper, but it's still costs a lot.
Add the more complex packaging (price, yields, size, ...) to it and IMO it makes less and less sense to go chiplets for desktop usage.
We need someone to put some numbers to the table here. Can someone do that?
Yes they could. I'm still sceptical they will do it with the first generation. Doing APUs with chiplets immediately complicates things considerably:APU in this design can also be chiplet based.
Consequences
1. You wish for longer depreciation to cover design cost. E.g. 14nm apu gets a platform refresh and will cover wsa obligations as well as the lower end market.
2. Your new products then needs to sell for more. Adaptability to more "niches" and faster to market helps that.
That's why AMD will probably go with something like this ...
For the time being this is certainly the case. After all we are still waiting for the upcoming Ryzen APU which will be at 12nm.I expect both low-end CPU and low-end GPU markets to be 12nm products
1. Building an interposer and at least 2-3 different chiplets is expensive. You can't really sell that anywhere near the price of a 2200G or a 2500U, which is the price level most OEMs are willing to pay for AMD models still.