64 core EPYC Rome （Zen2）Architecture Overview？

[deathBOB]

Chiplet confirmed, nice job everyone who made that prediction.

TL;DR explanation of why this is a big deal?

 

[Tuna-Fish]

TL;DR explanation of why this is a big deal?

It's a dramatically different approach. There is a standard way how the system architecture is laid out that AMD has used since 2003 and Intel since 2008, and this is a major change from it.

This new way of doing things has both advantages and disadvantages. Some of those we can guess, others will only show themselves in use. It's very interesting to speculate on them.

- For server customers, this means no more 4 numa nodes per socket. This will really help some important loads. Interestingly, since Intel just released Cascade Lake-AP, this means a complete role reversal. Except that AMD still has more cores per socket.

- Since they use infinity fabric connecting the CPU to the IO system, it means they can iterate on them independently. Especially with the rise of lower cost-to-iterate processes that are better for IO (like GF 22nm and 12nm), this might mean a lot more products targeting different workloads, all using the same chiplets for compute, but with a different IO die. The next Ryzen chips almost certainly use the same 7nm chiplets, just with an IO die aimed for desktop (possibly with GPU).

- Since they can iterate independently, they can now bring products to market for different IO standards without having to ship a new CPU die. I think this means AMD will be first out with DDR5 support, since they can just design a new IO die for that, and use the same chiplets for both AM4 and AM5 socket processors. Same goes with next-gen PCI-E.

 

[Saylick]

The real questions that remain now are the number of chiplets in EPYC 2, the IPC gain, cores/CCX, and if AMD is going to implement a EMIB interface, if it's still wiring in the substrate, or even an interposer to connect the IO die with the chiplets. Exciting times!

 

[PeterScott]

The next Ryzen chips almost certainly use the same 7nm chiplets, just with an IO die aimed for desktop (possibly with GPU).

I doubt that.

While chiplets look like a good tradeoff for TR/Epyc that already have multi-chip latency issues, and are aimed at markets where those latencies don't really matter, Ryzen is a desktop part, where latency does matter and there are currently no multi-chip latency penalties.

A chiplet design for Ryzen is really not a great choice. AMD should, and hopefully feels they have enough market, and enough money to do a separate monolithic die for desktop.

Or maybe they desktop Part will only be the APU this time, but with 8 Cores.

 

[Saylick]

I doubt that.

While chiplets look like a good tradeoff for TR/Epyc that already have multi-chip latency issues, and are aimed at markets where those latencies don't really matter, Ryzen is a desktop part, where latency does matter and there are currently no multi-chip latency penalties.

A chiplet design for Ryzen is really not a great choice. AMD should, and hopefully feels they have enough market, and enough money to do a separate monolithic die for desktop.

Or maybe they desktop Part will only be the APU this time, but with 8 Cores.

Agreed. The extra die space to integrate all of the necessary IO for the Ryzen SKUs is worth it instead of making another smaller IO die just to have a chiplet approach with Ryzen.

 

[DisEnchantment]

A lot of the speculation went well

Not sure if this a 64 core part.

But at least we are on the right track

• 14nm IO Chiplet
• 7nm Chiplets
• MC on the IO die
• 8 cores per Zen 2 die (not sure if per CCX)
• 2x fp compared Zen1
• Improved front end (also according to Agner, Zen1 backend is bottlenecked by the front end)
• 33% better memory bandwidth (due to higher memory speed?)

That IO die looks fairly huge.

I have to say a lot of those improvements they showed today left a patent trail if you have the patience to dig through.

 

[DrMrLordX]

That IO die looks fairly huge.

Might be from that fat L4 cache on there . . .

 

[Tuna-Fish]

That's definitely a SP3 socket. Sadly, I need to run now, but is there any chance some kind soul here could work out the dimensions of those chips on there?

 

[HurleyBird]

Might be from that fat L4 cache on there . . .

Or maybe a GPU, or maybe there are links for two more chiplets (to be placed at left and right middle) for a hypothetical 80-core version. Or some combination of the above

 

[deathBOB]

It's a dramatically different approach. There is a standard way how the system architecture is laid out that AMD has used since 2003 and Intel since 2008, and this is a major change from it.

This new way of doing things has both advantages and disadvantages. Some of those we can guess, others will only show themselves in use. It's very interesting to speculate on them.

- For server customers, this means no more 4 numa nodes per socket. This will really help some important loads. Interestingly, since Intel just released Cascade Lake-AP, this means a complete role reversal. Except that AMD still has more cores per socket.

- Since they use infinity fabric connecting the CPU to the IO system, it means they can iterate on them independently. Especially with the rise of lower cost-to-iterate processes that are better for IO (like GF 22nm and 12nm), this might mean a lot more products targeting different workloads, all using the same chiplets for compute, but with a different IO die. The next Ryzen chips almost certainly use the same 7nm chiplets, just with an IO die aimed for desktop (possibly with GPU).

- Since they can iterate independently, they can now bring products to market for different IO standards without having to ship a new CPU die. I think this means AMD will be first out with DDR5 support, since they can just design a new IO die for that, and use the same chiplets for both AM4 and AM5 socket processors. Same goes with next-gen PCI-E.

How is it different than an external north bridge or memory controller like we had a long time ago?

 

[PeterScott]

A lot of the speculation went well

Not sure if this a 64 core part.

But at least we are on the right track

• 14nm IO Chiplet
• 7nm Chiplets
• MC on the IO die
• 8 cores per Zen 2 die (not sure if per CCX)
• 2x fp compared Zen1
• Improved front end (also according to Agner, Zen1 backend is bottlenecked by the front end)
• 33% better memory bandwidth (due to higher memory speed?)

That IO die looks fairly huge.

I have to say a lot of those improvements they showed today left a patent trail if you have the patience to dig through.

I think that is obviously 64 core part. It has 8 chiplets, which undoubtedly have 8 cores each, giving the rumored 8+1 config.

But yeah that IO die is monstrous. I also assume it must have a big L4 cache.

 

[DisEnchantment]

Sorry ...

 

[Atari2600]

I doubt that.

While chiplets look like a good tradeoff for TR/Epyc that already have multi-chip latency issues, and are aimed at markets where those latencies don't really matter, Ryzen is a desktop part, where latency does matter and there are currently no multi-chip latency penalties.

A chiplet design for Ryzen is really not a great choice.

Could you please explain the mechanics of why you think latency will get markedly worse?


L1 ~ same depending on core design
L2 ~ same depending on core design
L3 = vastly improved due to all 8 cores sharing L3 cache and not having to go through crossbars clocked at DDR4 rate (Zen1).
L4 = doesn't exist on Zen1, might exist on Zen2. Thus can only be an improvement.
DRAM ~ approximately the same. The interface between the IO chip and the CCX chiplet now does not need to run at MEMCLK, I'd expect they are instead trying to tie it to core clock. So you are looking at a service time from CCX to IO chiplet that would more resemble the L2 times of Zen1+ than the L3. Even assuming it isn't, compare the Zen1+ L3 latency to DRAM (note y-axis is logarithmic).

L3 ~ 30 cycles
DRAM ~ 300 cycles

So going through the I/O chip at worst increases DRAM latency from ~300 to ~330 cycles.... and I'd wager that using the I/O chiplet to decouple on socket infinity fabric from MEMCLK has allowed AMD to really pull that L3 latency down - so that 30 might be more like 20. They also talk about improved memory speeds.

 

[Atari2600]

8 Core CCX confirmed

Whats that?

Looks more like Naples than anything else...?

 

[PeterScott]

Could you please explain the mechanics of why you think latency will get markedly worse?

Not every solution makes sense everywhere. Chiplets are good for TR/EPYC, not so good for desktop.

Integrated MC as opposed to Memory controller on another chip. There is a latency penalty for going off chip.

For a small desktop chip, chiplets should have worse latency and be less cost effective.

 

[HurleyBird]

Whats that?

Looks more like Naples than anything else...?

Yup, that's Naples. Doesn't confirm anything.

 

[itsmydamnation]

WOW so i was wrong....rofl.



did anyone else notice it looks like the chiplets are in pairs of two on a interposer???

edit: also we need conformation about the load store, "12:53PM EST - Improved pipeline, DOuble loading point and load store"

i hope this means 4 load and 2 store ports, but im gussing it just means 2/1 256bit load/store ports

 

[DisEnchantment]

What does this mean Doubles the BW/Channel for the same number of channels?
Increased frequency or just efficient usage?

 

[Atari2600]

Not every solution makes sense everywhere. Chiplets are good for TR/EPYC, not so good for desktop.

Integrated MC as opposed to Memory controller on another chip. There is a latency penalty for going off chip.

For a small desktop chip, chiplets should have worse latency and be less cost effective.

That is not an explanation of the mechanics of why the latency will be worse beyond a high level assumption that going through an IO Controller will be markedly worse.

I have pointed out (with measured numbers) that your high level assumption does not hold up.

I await your explanation for why it will be so much worse it will matter.



As for why AMD won't design a desktop die, simples, cost. Any marginal (and they are very marginal) gains AMD would make in cutting DDR latency by a few percent for Ryzen7 would be lost in the mask cost and in requiring dedicated wafers for desktop rather than flexibility in wafer starts.

A redesign for Ryzen7 also means a redesign for Ryzen3. Which means 3 masks, not 1. Keeping the same 8 core unit allows the same 7nm mask to be reused and the I/O Controller switched out.


The market does not revolve around desktop, regardless of how much some folks on here get tunnel vision and think it does.

 

[HurleyBird]

I'm don't know if that's actually an interposer you're seeing. It could just be the filler that helps hold the chips in place. Oh the other hand, the chips are very close to one another.

 

[tamz_msc]

WOW so i was wrong....rofl.



did anyone else notice it looks like the chiplets are in pairs of two on a interposer???

edit: also we need conformation about the load store, "12:53PM EST - Improved pipeline, DOuble loading point and load store"

i hope this means 4 load and 2 store ports, but im gussing it just means 2/1 256bit load/store ports

Maybe it's just how the thing is packaged? Doubled Load/store could also mean 64B/cycle up from 32B/cycle.
EDIT: Are we both saying the same thing when you mention 4 load and 2 store ports and 64B/cycle?

 

[HurleyBird]

What does this mean Doubles the BW/Channel for the same number of channels?
Increased frequency or just efficient usage?

That's just for PCIe, not the memory controllers.

 

[itsmydamnation]

Maybe it's just how the thing is packaged? Doubled Load/store could also mean 64B/cycle up from 32B/cycle.
EDIT: Are we both saying the same thing when you mention 4 load and 2 store ports and 64B/cycle?

see what i want is 4x128 load and 2x128 store a cycle
what i think it will be is 2x256 and 1x256 store a cycle

What Ian wrote in the live steam could be interpreted both ways (to me anyway).

 

[tamz_msc]

see what i want is 4x128 load and 2x128 store a cycle
what i think it will be is 2x256 and 1x256 store a cycle

What Ian wrote in the live steam could be interpreted both ways (to me anyway).

Ah, I was thinking of cache b/w. I suppose it might have been increased as well, given the increased FP performance.

 

[darkswordsman17]

What does this mean Doubles the BW/Channel for the same number of channels?
Increased frequency or just efficient usage?

Not sure exactly, but PCIe 4 doubles up PCIe 3 (and 5 will double up 4). Not sure what latency changes (where for instance, memory bandwidth has increased, but I believe latency has as well).