I'll just pretend I understood the question, and we'll take it from there.Originally posted by: glugglug
Vee: is "52-bit" addressing a clean linear mode or is that segmented crap like PAE to get the extra 4 bits?
(I think AMD64 supports PAE inside legacy mode) But no, we are free from Intel's dreaded segmented addressing. 64-bit mode does the opposite to Physical Address Extension. It goes from a larger virtual space (64/48) (48-bit in K8) to a smaller physical space (52/40) (40-bit in K8).
In short, no, there's a minimum of "segmented crap". It's linear in everything that matters, and can be.
The AMD86-64 architecture as defined, supports physical addresses up to a maximum of 52 bits (4 Petabytes). In that case we are using all 64 bits for linear virtual addresses. We can't use more than a total of 4 Petabytes, of course, but we can have the memory blocks of any size (well...) anywhere in the 64-bit range. But all that is just AMD86-64 theory.
In practice (in the K8 cpus) we are limited to physical addresses up to a maximum of 40 bits (1 Terabyte). That also limits our linear virtual address range to the lower 48 bits. As before, we cannot use more than 1 Terabyte, but again we can have the memory blocks anywhere in the 48-bit range.
The mapping of addresses from the 48-bit linear space to 40-bit physical space is done by a paging mechanism. I guess the principle is similar to Windows32's mapping of 32-bit linear virtual addresses to physical addresses in 4KB pages.
This is sound since it allows the OS to avoid fragmentation of physical ram, and also allows for storage of memory pages in swap.
In the case of segmented legacy modes, in 'compatibility mode', these are first translated to a linear address with segmentation similar to original modes. However, I think the segment selectors are used directly, combined with the address, to form the linear address. No page descriptors, thus. There seems to be tons of options here though, and we'll have to read up on Windows64 to understand exactly how MS have implemented this. Anyway we now have a linear address, from the segmented mode. This linear address now corresponds to 64-bit (48-bit) mode's linear virtual address. And is then mapped by the same paging mechanism to physical address.
I think we must read the details, about the paging to physical pages, in MS Windows64 documentation, (or Linux kernel stuff).
There is also 'AMD64 Programmers Manual, Volume 2: System Programming'
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf
But I suspect the OS will be the important part in this, and the cpu manual will only provide us with a headache in this case.
- Sorry, I do not have a link to a suitable Windows86-64 document.