Hyperscalers do get substantial discounts (highly doubtful it is even close to 80% for Zen2/3 today), but they are also still a smaller part of the TAM and this also doesn't apply to SKUs like a (rumored) 4 stack Epyc which will carry a large premium that, again, the people who need it will be willing to pay.
The Hyperscalers are the customers AMD is having the most success with, as far as market penetration, and other segments are much slower to move. The other segments don't have discounts as deep as hyperscalers.
No one's arguing to chase GM at all costs, but throwing silicon at the problem disregarding the cost of the silicon is equally foolish and has rarely made a successful company. Even the 1000 mm2 you have mentioned is void of context as 40% of that size is on an old and much cheaper process and the rest is split into high yielding chiplets, so AMD can afford to throw much more silicon into a product than Intel in this context.
AMD kept throwing silicon at the EPYC chips as long as performance kept scaling well and until the power limit was hit. AMD didn't decide to randomly stop half way.
Old Intel would have stopped half way under theory that the extra 32 cores would have lower GMs.
BTW, the cost of that SRAM silicon is most likely lower than cost of the IO die silicon, per mm2.
Whatever the yields for stacking 4 hi are, the premiums will be absorbed by the Epyc customers who need it. I'm not confident the same can be said in the consumer market.
I don't think yields will be an issue at all.
TSMC is getting excellent yields on N7, even better on N6. SRAM will get as close to 100% as you can get. Only good die are entering assembly, and there will most likely be way to isolate and disable bad layers.
If Intel really just wanted to throw silicon at the problem, they would have released 8C Ice Lake or 8C Tiger Lake much earlier. They didn't because it was too costly given their yields at the time.
Having problem yielding good dies means you don't have a lot f silicon to throw at the problem.
They easily could have, but would have taken a major hit in costs. Likewise, AMD could easily buy up TSMC risk production and be way ahead of Intel with an even bigger process lead than they've enjoyed the last couple of years, but again, they didn't because the cost would have been too high.
It has been only a year since AMD became very profitable. A lot of the decisions about product line up and risk profile of products were made when AMD was much poorer, and the market share in more lucrative segments was very low. So AMD did not have a lot of options as far as buying up risk production at TSMC.
AMD is still quite conservative and risk averse about future products.
What most people can't seem to get is that V-Cache is a very low risk, high reward move. AMD can get N5 or even N3 level performance product out of TSMC N7 node.
There needs to be a proper balance and understanding of how much your customer is willing to pay.
Nvidia is charging - and successfully selling a gaming graphics card for $1,500. Nvidia is going to ridiculous lengths to get this type of product.
The trick is to have a product.
Going for an epeen win, price be darned is a strategy I really don't think AMD is going to play into. The only way I see AMD going this route is if ADL absolutely destroys Zen 3 and Zen 4 is at least a year or more away after ADL and ADL is available with decent volume.
The Halo ADL product with DDR5, released in 2021 is going to destroy Zen 3.
And Zen 4 is more than a year away from today.
If that's the case, then maybe they start offering a lot more cache to try and stay competitive and not be crushed in sales, but I really doubt this will be the case.
Or to keep ASPs from crushing.
Luckily, AMD has a tool in its tool chest with which performance can be increased gradually, with $6 increments, up to the level needed to beat the ADL