In my opinion, your expectations are too high. According to the Chinese forum about GoldenCove and Cortex X2, Zen 4 is a 20-25% increase in IPC.
At the risk of turning this into the Zen4 thread, I think Chips and Cheese (https://chipsandcheese.com/2021/02/05/amds-past-and-future-cpus/) is up till now the only one who has dared to give an actual number (29% IPC uplift). At the time I'd be ready to declare that nonsense for being too early for a CPU that still had 18 months until release but they have been writing some solid (though non-leaking) content after so I'm kinda more on the fence now.
I think it is attractive to believe higher numbers because Intel increasing IPC At almost 20% for 2 gens in a row on desktop (though Cypress Cove had other issues) within a single year and Zen4 looking like it is taking 2 years. Belief doesn't make a product though.
I believe that a lot of the structures that could be changed are not really sized in the gigabyte leaks (stuff like various queues and such, like e.g the ROB or the internal register file), so there are definitely possibilities, but also very little hints what changes they did make and how much those help.
Up
Sunny / CypressCove and GoldenCove are, in fact, not one year apart.
Project work:
SunnyCove 2016-2018(relase 2019)
GoldenCove 2018-2020(relase 2021)
WillowCove (x86 SunnyCove with a redesigned cache subsystem) and RaptorCove were certainly working in parallel.
I think work was going on in parallel on RedwoodCove which was finished in June. Perhaps it was RedwoodCove that work lasted from 2017, which would give 3-4 years of design.
The only certainty is SumnyCove, to which Intel admitted that the work started in 2016, and assuming 18-month design cycles, it will be completed in 2018 and made in silicon to be released in 2019.
I don't think you would see AMD do that. They would just wait until Zen 4. Threadripper doesn't have any competition and won't until Sapphire Rapids-X shows up and who knows when that will be.
I haven't seen a single soul on this forum suggesting otherwise.Threre IS going to be a Zen 3 Threadripper (vanilla and/or 3D).
A larger L2 would also incur a power hit. So the question is, would the larger L2 with an existent L3 be able to justify the performance improvement over smaller L2 with a virtual L3 scheme? Maybe I'm biased but my mind says that the virtual L3 will conserve more power while delivering better performance, unless the workload is so multicore friendly that all the cores are max utilized and managing the virtual L3 with their workload leads to performance degradation. That might be the case up to a certain number of cores. But very few workloads scale perfectly to a large number of cores so a virtual L3 scheme might end up boosting performance more often than not. Am I making sense?While it certainly is a latency improvement, it's going to be a power hit. Plus, it's adding overhead to adjacent L2 cache management.
I can see AMD going for a larger L2, to the order of 2MB even, and using 3D stacking for all L3 cache, for their desktop chips.
While it certainly is a latency improvement, it's going to be a power hit. Plus, it's adding overhead to adjacent L2 cache management.
I can see AMD going for a larger L2, to the order of 2MB even, and using 3D stacking for all L3 cache, for their desktop chips.
A larger L2 would also incur a power hit. So the question is, would the larger L2 with an existent L3 be able to justify the performance improvement over smaller L2 with a virtual L3 scheme? Maybe I'm biased but my mind says that the virtual L3 will conserve more power while delivering better performance, unless the workload is so multicore friendly that all the cores are max utilized and managing the virtual L3 with their workload leads to performance degradation. That might be the case up to a certain number of cores. But very few workloads scale perfectly to a large number of cores so a virtual L3 scheme might end up boosting performance more often than not. Am I making sense?
That would be a very interesting comparison.If they got rid of L3, the L2 would have to grow much more so you would need to compare a Zen core with a bit more L2 cache than current + L3 cache (+stacks) versus a Zen core with comparatively huge L2 caches (possibly +stacks) and virtual L3.
What and where did you read about it that's amazing? I only read Ian's take, and honestly having previously read plenty cache related patents by AMD I'm honestly not seeing how it's anything special, never mind "magic" as in Ian's words. AMD's patents point to Zen moving in a pretty similar direction.IBM Telum's virtual L3 concept is pretty amazing.
I think it is attractive to believe higher numbers because Intel increasing IPC At almost 20% for 2 gens in a row on desktop (though Cypress Cove had other issues) within a single year and Zen4 looking like it is taking 2 years. Belief doesn't make a product though.
That's very encouraging to hear. I do wish Zen 4 has virtual cache.AMD's patents point to Zen moving in a pretty similar direction.
But, what are we really expecting from Zen3 Threadripper? I'm still not expecting a lot from Zen3 TR over Zen2 TR. The big gain from Zen3 seems to have been ST tasks. Maybe when dealing with programs that exist in the 8 thread realm, you might realize significant gains, as there can be one or two threads per CCD, but anything that would heavily load all the cores probably won't see worthwhile gains. Now, a Zen3D based product might be a bigger deal, but, I have to think that the demand there would be massive for their supercomputer projects, or, for those "Licensed by the core" products where they can have a product that has 8 CCDs, each with a maximum clock single core, and a 4 stack of cache, giving 288MB of L3 per core.
While it certainly is a latency improvement, it's going to be a power hit. Plus, it's adding overhead to adjacent L2 cache management.
I can see AMD going for a larger L2, to the order of 2MB even, and using 3D stacking for all L3 cache, for their desktop chips.
Keep in mind that the a portion of Zen 4's IPC increase is owed to the new IOD.
Of course, it's possible that the new IOD still features links for 3 CCDs, in which case they could be holding the 24-core in reserve.
Odds are that they also have Zen 4-3D in reserve.
I don't see any sort of advantage to having L2 on the stack.
I read that as more of a "this is where the technology is capable of going" and not as "this is where we are definitely going on our roadmap with it" kind of thing. Yes, it can be done, but should we?See smack middle of slide:
AMD details its 3D packaging technology at Hot Chips 33 | OC3D News (overclock3d.net)
AMD has ambitious packaging ideas, it seems.
Depends on the costs. Going MCM with Zen and chiplets with Zen 2 allowed AMD to achieve something that they couldn't have done with a monolithic equivalent. There may come instances where the same is true for stacked dies.I read that as more of a "this is where the technology is capable of going" and not as "this is where we are definitely going on our roadmap with it" kind of thing. Yes, it can be done, but should we?
That's a lot of distance to cover for an L2 cache. That's also a lot more connections that will need to be driven between the die.
I don't see any sort of advantage to having L2 on the stack.