They basically announced 3 new server CPUs over the next 18 months. Crazy when you consider how competitive Milan already is. Sapphire Rapids needs to be really good for Intel.
Why the latency hit off die? Going vertical should place it closer, on average.I'm beginning to think that we're going to be seeing parts from AMD that have substantially larger L2s and no L3 at all on the ccd with all the L3 on a stacked die. The larger L2 hiding the slight latency hit of the L3 being off die.
Yeah, AMD is willing to lose some desktop share in favor of having more CCDs for server.They basically announced 3 new server CPUs over the next 18 months. Crazy when you consider how competitive Milan already is. Sapphire Rapids needs to be really good for Intel.
Hopefully the desktop gets more than the scraps. But with the repeated delay or disappearance of Chagall it seems they are focused on servers.
"Milan-X" up to 50% faster and for some simulation software/workload up to 80% faster.
I don't see how they can release a next gen zen4 Epyc without this 3D cache.
We knew games would be +15% but seems for server applications it will even have a bigger impact !!
They add an X for 3D cache, uhmmm: 5900X² ?
I've seen it referenced a few times on these forums that there is a SLIGHT latency hit from 3d stacking the L3 cache. It's either related to having expanded tables for the larger size, or the fact that the electrical distance from each core to each L3 cell is still physically slightly longer (though, we're still talking extremely tiny amounts. With the clock speeds associated, it does matter).Why the latency hit off die? Going vertical should place it closer, on average.
Some compute-oriented benchmarks show only ~2% gains from all the cache. See the new Azure VMs benches."Milan-X" up to 50% faster and for some simulation software/workload up to 80% faster.
I don't see how they can release a next gen zen4 Epyc without this 3D cache.
We knew games would be +15% but seems for server applications it will even have a bigger impact !!
They add an X for 3D cache, uhmmm: 5900X² ?
As has been said time and time and time and time and time again, if your workload isn't memory bound, you're not going to get a significant performance boost.Some compute-oriented benchmarks show only ~2% gains from all the cache. See the new Azure VMs benches.
So don't be surprised by a huge disparity among the benchmarked V-Cache gains. It all depends on the workload.
Interesting link. I wonder most how much cache helps in typical web applications. We'll see with Zen3D.Some compute-oriented benchmarks show only ~2% gains from all the cache. See the new Azure VMs benches.
So don't be surprised by a huge disparity among the benchmarked V-Cache gains. It all depends on the workload.
It's definitely due to the expanded tables for larger size. There's a reason why caches are usually relatively tiny, smaller tables to scan through improve latency. AMD apparently being able to massively expand L3$ with a rather negligible latency hit shows both that they found a way to scale it out massively and that Zen 3's L3$ design was designed to accommodate 3D V-Cache from the start even if as a product it arrives this late. Will be interesting whether they can apply part of that experience to L2$ as well.I've seen it referenced a few times on these forums that there is a SLIGHT latency hit from 3d stacking the L3 cache. It's either related to having expanded tables for the larger size, or the fact that the electrical distance from each core to each L3 cell is still physically slightly longer (though, we're still talking extremely tiny amounts. With the clock speeds associated, it does matter).
"Milan-X" up to 50% faster and for some simulation software/workload up to 80% faster.
I don't see how they can release a next gen zen4 Epyc without this 3D cache.
We knew games would be +15% but seems for server applications it will even have a bigger impact !!
They add an X for 3D cache, uhmmm: 5900X² ?
This is one of those seemingly minor improvements, often overlooked by enthusiasts like us, that go a long way towards improving performance. A real secret sauce item.It's definitely due to the expanded tables for larger size. There's a reason why caches are usually relatively tiny, smaller tables to scan through improve latency. AMD apparently being able to massively expand L3$ with a rather negligible latency hit shows both that they found a way to scale it out massively and that Zen 3's L3$ design was designed to accommodate 3D V-Cache from the start even if as a product it arrives this late. Will be interesting whether they can apply part of that experience to L2$ as well.
Zen4 is 25% higher performance per Core, you add more Cores and higher bandwidth you can still see Zen4 EPYC>>MilanX>Milan for general purpose CPUs. For sure there will be Zen4 3D Cache options down the line for special purpose CPUsI don't see how they can release a next gen zen4 Epyc without this 3D cache.
I think AMD was slighly underselling impact of V-Cache for games and we will see couple of outliners showing way more than >15% improvement. One thing is certain though, 3D rendering will not be getting any boost at all with new cache, Photoshop and general productivity on another hand ...
I think you're just trying to get a rise out of people by posting utter nonsense, and I won't be one who falls for it.
And the Intel CPUs aren't even out yet (or reviewed), so you have ZERO proof of what you keep claiming. Yet here you are post after post after post like you are in some kind of inner circle with access to this info.
But you do you. Good job!
From the sound of it, if a person can wait 2-3 days, all Zen 3 CPUs should be free of charge.
I guess I'll keep an eye out for that Newegg/Amazon clearance (in between watching the previously mentioned Biden climate change speech). Hopefully all the B550 and X570 motherboards will be in the same boat as well.
Why even bother with zen3D, when margins and demands for GPUs are at a record high?
If you have limited 7nm wafers and you are guaranteed to sell every GPU you make. Is there any reason to focus on CPUs in this market?
I can understand if AMD skips zen3D and goes directly to zen4.
We don't know where all the GPU margins go. AMD sells to AIB at a set price that is related to MSRP. Those prices then get inflated and profits pocketed by others, not AMD.
If you start from MSRP, and cost of silicon, CPUs have a higher margins for AMD than GPUs. For example:
- Zen 3 die is 80mm2. 5800x had (before new discounts) an MSRP of ~450
- Navi 23 die is ~240mm2. 6600/6600 XT MSRP is ~350
So 3x silicon, lower price, and there are a lot of extra components that go into making a GPU (vs. CPU).
One thing to keep in mind
Zen3D lets AMD delay Zen4 on high-end desktop interminably until they have enough "failed"/high leakage CCDs from Genoa production to roll out Raphael cost-effectively. Assuming Raphael even follows the Zen2/Zen3 model which is still not certain! Regardless, AMD may save a lot of time/trouble/sweat and make a ton of extra money by provisioning the majority of their N5 wafers for Genoa and CDNA2/Mi200. Zen3D can be sold as a loss leader just to maintain (or grow) desktop market share.
Really? I had heard it would be hybrid N7 and N5. If Mi200 is N7-only, that saves more N5 wafers for Genoa.
Do we think that AMD would attempt die recovery on the Cache dies? For example, use the full 64MB L3 dies for the 8C parts, and if they have a non-trivial amount of Cache dies that have a bad cell or two, produce 32 or 48MB L3 dies for bonding to the 6 core CCDs?
Oh, you decided to come back?Here child, you have a lot to learn.
AMD's Ryzen 5000 CPU Series Is Creeping To A More Affordable Price Point (wccftech.com)
Probably not. Pretty sure AMD has said publicly that if they actually do release Zen3D that it will be 12c and 16c parts only. Would be nice if I'm wrong, but . . .
Then something does not add up. How AMD could have >24% X86 market share in Q3 when notebook is 22% and server less than 20%? The third part of the equation is desktop.
I'm beginning to think that we're going to be seeing parts from AMD that have substantially larger L2s and no L3 at all on the ccd with all the L3 on a stacked die. The larger L2 hiding the slight latency hit of the L3 being off die.