Can someone with more knowledge on TSMC 7nm HD process works Help me out here?
According to TSMC their High Density optimized SRAM cell libraries are 0.027 um^2. But if that was the case the L3$ Die on the 5800X3D which is about 36 mm^2 should have 256 MiB of ram..
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I am basing my math on Anandtech article about TSMC 5nm(where they calculate um^2 x Megabit to get mm^2 die area)
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I think that the numbers posted by Anandtech as far as mm^2 per Megabyte are off..
Here is something better, but still is half as Dense as the L3$ 3D Cache.
スマートフォンやタブレットなどに向けた高性能大規模SoC(System on a Chip)の製造技術が、急速に微細化しつつある。次世代に相当するのは7nm世代のCMOSロジック技術である。量産開始のタイムスケジュールは今のところ、2018年とされている。以前は7nm世代の量産開始は2019年以降とされていたのが、昨年(2016年)になって前倒しにされた。
pc.watch.impress.co.jp
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How is TSMC pulling the L3$ IO Die Densities? It boggles my mind.