7nm EUV in 2019

[raghu78]

TSMC confirms 7nm EUV in 2019

http://www.tsmc.com/uploadfile/ir/quarterly/2016/4hBX9/E/TSMC 4Q16 transcript.pdf

Excerpt from TSMC Q4 2016 earnings call

Mehdi Hosseini - Susquehanna Financial Group - Analyst
Okay. Then when we look into 7 nanometer and some of your competitors have a different definition of 7. Can you help us understand how your N7, compete and is positioned against your competitors?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Senior Director, TSMC Corporate Communications Division
So Mehdi is saying that our 7 nanometer definition is different from other companies' 7 nanometer definition, so how do we compete at 7?

Morris Chang - Taiwan Semiconductor Manufacturing Company Ltd - Chairman
Our 7 nanometer definition is different from somebody else's? Well, I'll let Mark answer.

Mark Liu - Taiwan Semiconductor Manufacturing Company Ltd - President and Co-CEO
I wouldn't want to comment on other people's 7 nanometer. Our 7 nanometer is under qualification now and it will be qualified as according to plan from the end of first quarter. And we have already more than 20 customers design-in on this 7 nanometer and this year alone we estimate will be 15, 20 tapeouts already. So this is our momentum build so far on a seven nanometer and no other competitor is getting to this stage of this leading edge technology. So we have -- we are to -- remember I mentioned last time we'll have 5 nanometer two years from now and forget about the name. That will be a full node shrink and that will sit competing well with any technology come out at that time. Okay, let me add some on 7 nanometer. We will maintain our 7 nanometer competitiveness just like we do on 28 and 16. We will have a technology currently planned as 7 nanometer but with the EUV insertion in the second year of 7 nanometer, just one year -- approximately one year after. And that can greatly simplify the process and without increase the cost. And that is if customer can take advantage of minor design it can further reduce their density -- increase their density and reduce their die cost. That is our plan to maintain that competitiveness of the 7 nanometer the year after. So we think 7 nanometer is a well adopted node by all the customers and we plan for the subsequent technology to shore up the demand continuously. And we hope to use this technology -- I mean the second-year technology to prepare for the EUV production experience for the full fledged EUV technology on 5. Then our customers can have a very hopefully smooth getting to from our 7 to our 5 nanometer technology. So that is how we maintain our technology competitiveness.

Mehdi Hosseini - Susquehanna Financial Group - Analyst
May I ask a clarification question?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Senior Director, TSMC Corporate Communications Division
Sure.

Mehdi Hosseini - Susquehanna Financial Group - Analyst
I think if I heard you correctly is you will insert -- if I heard you correctly you said you will insert EUV in this second year of your 7 nanometer, which suggests to me that you may actually be able to commercialize (technical difficulty) conclusion here?

Elizabeth Sun - Taiwan Semiconductor Manufacturing Company Ltd - Senior Director, TSMC Corporate Communications Division
Mehdi, I'm afraid that your voice was broken at some point in time. Can you please repeat? We heard you, that you said that we will insert EUV in the second year of 7 nanometer and then you had something but it was cut off. Can you repeat that part?

Mehdi Hosseini - Susquehanna Financial Group - Analyst
Sure. Yes, sorry about that. I just wanted to make sure I understand the EUV commentary correctly. You said that you will insert EUV in the second year of 7 nanometer. That suggests to me that you may actually be able to insert EUV before competitors that have said insertion would happen at 5. Is that the right conclusion as we compare and try to better understand your competitiveness at 7 nanometer?

Mark Liu - Taiwan Semiconductor Manufacturing Company Ltd - President and Co-CEO
Yes, we will commercialize the 7 EUV in the second year of our 7-nanometer production. I wouldn't comment on when will our competitor insert their EUV. That is -- I don't intend to do the comparison here.


Another article about EUV at 7nm

http://semimd.com/blog/2017/01/19/innovations-at-7nm-to-keep-moore’s-law-alive/

TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.

Huiming Bu, who presented the IBM Alliance 7nm paper at IEDM, said “EUV delivers significant depth of field (DoF) improvement” compared with the self-aligned quadruple (SAQP) required for the metal lines with immersion scanners.

A main advantage for EUV compared with multi-patterning is that designs would spend fewer days in the fabs. Speaking at ISS, Gary Patton, the chief technology officer at GlobalFoundries, said EUV could result in 30-day reductions in fab cycle times, compared with multiple patterning with 193nm immersion scanners, based on 1.5 days of cycle time per mask layer.


TSMC's 7nm EUV products should be out in H2 2019. AMD has a lot of choice and flexibility now that they have amended WSA. It would be interesting to see AMD CPUs manufactured at TSMC 7nm EUV go up against Intel 10nm CPUs. Intel is going to face the most stern competition it has ever faced from TSMC in the process node race. TSMC has also said it intends to ramp 5nm with EUV in 2020.

 

[Phynaz]

TSMC's 7nm EUV products should be out in H2 2019. AMD has a lot of choice and flexibility now that they have amended WSA. It would be interesting to see AMD CPUs manufactured at TSMC 7nm EUV go up against Intel 10nm CPUs. Intel is going to face the most stern competition it has ever faced from TSMC in the process node race. TSMC has also said it intends to ramp 5nm with EUV in 2020.

AMD isn't going to be producing (selling) chips manufactured using EUV in 2019. From your own post;
"EUV is under development (at TSMC), and we will use 7nm as the test vehicle."

ASML, who is TSMC's supplier of lithography tools has stated they don't have production ready tooling yet.

Also, the WSA still hangs over AMD's head. It's not like AMD's annual re-negotiation has removed that noose from their neck. Hector Ruiz, the CEO that keeps on giving.

 

[raghu78]

AMD isn't going to be producing (selling) chips manufactured using EUV in 2019. From your own post;
"EUV is under development (at TSMC), and we will use 7nm as the test vehicle."

ASML, who is TSMC's supplier of lithography tools has stated they don't have production ready tooling yet.

Also, the WSA still hangs over AMD's head. It's not like AMD's annual re-negotiation has removed that noose from their neck. Hector Ruiz, the CEO that keeps on giving.

dude you are selectively quoting what you want to drive your narrative. TSMC confirmed the 7 EUV in second year of 7nm volume production. Since the 7nm HVM ramp is in H1 2018 that means TSMC 7 EUV will ramp in 2019. Its obvious since 5nm EUV is scheduled for ramp in 2020 and TSMC would want to introduce EUV on a mature 7nm node and use the experience for a smooth 5nm EUV ramp a year later.

 

[Arachnotronic]

dude you are selectively quoting what you want to drive your narrative. TSMC confirmed the 7 EUV in second year of 7nm volume production. Since the 7nm HVM ramp is in H1 2018 that means TSMC 7 EUV will ramp in 2019. Its obvious since 5nm EUV is scheduled for ramp in 2020 and TSMC would want to introduce EUV on a mature 7nm node and use the experience for a smooth 5nm EUV ramp a year later.

EUV in production really is a function of what the semicaps are able to pull off (industry wide thing, not just any individual semi mfg), and it has been "just around the corner" for many many years. It would be prudent to wait for things to actually start happening and for production equipment to start getting delivered before getting too excited.

 

[Phynaz]

dude you are selectively quoting what you want to drive your narrative. TSMC confirmed the 7 EUV in second year of 7nm volume production. Since the 7nm HVM ramp is in H1 2018 that means TSMC 7 EUV will ramp in 2019. Its obvious since 5nm EUV is scheduled for ramp in 2020 and TSMC would want to introduce EUV on a mature 7nm node and use the experience for a smooth 5nm EUV ramp a year later.

No, I'm pointing out that you have come to the wrong conclusion by ignoring what you even quoted.

Here's a great idea, read what TSMC presented at ISSCC, and read ASML's earning reports where they state how many NXE:3400 systems they have sold (hint: six).

Heck, ARM doesn't even have a EUV compatible design yet, I have no idea how you expect AMD to have one.

 

[raghu78]

EUV in production really is a function of what the semicaps are able to pull off (industry wide thing, not just any individual semi mfg), and it has been "just around the corner" for many many years. It would be prudent to wait for things to actually start happening and for production equipment to start getting delivered before getting too excited.

ASML customers like TSMC have a better idea than you and me before making a public statement on an earnings call.

No, I'm pointing out that you have come to the wrong conclusion by ignoring what you even quoted.

Here's a great idea, read what TSMC presented at ISSCC, and read ASML's earning reports where they state how many NXE:3400 systems they have sold (hint: six).

Heck, ARM doesn't even have a EUV compatible design yet, I have no idea how you expect AMD to have one.

http://seekingalpha.com/article/4037520-asml-holding-n-v-2016-q4-results-earnings-call-slides

Interestingly ASML expects EUV introduction at 7nm node. Read slide 17 titled " Commitments to EUV production insertion" which says "Initial customer manufacturing targeted for 7nm logic and mid 10-nm DRAM node".

I will not be surprised to see the Apple A13 manufactured at TSMC 7nm EUV and come out in late 2019.

 

[Phynaz]

Apple - yes, AMD - no.

 

[raghu78]

Apple - yes, AMD - no.

Thats a matter of opinion. Nvidia and AMD launched their 16/14nm GPUs about a month apart and roughly 9 months after Apple. With Zen and their successors allowing AMD to compete in the high end server and entusiast desktop market AMD would not be short on cash to move to the latest nodes at the earliest possible. Heck even when they were bleeding money they were able to move to FINFET GPUs at the same time as Nvidia. I expect Zen/Zen+ and future revisions to allow AMD to regain market share and Vega/Navi should allow them to do much better than they did during the Maxwell generation where they hit sub 20% market share. AMD has always adopted the latest nodes as soon as possible. TSMC are executing phenomenally well and AMD has the flexibility to choose them for manufacturing their products. They do have volume commitments with GF but AMD should not have problem meeting them as there are a whole lot of products - from entry level to high end desktop/notebook APUs, desktop CPUs, server CPUs, server APUs , console APUs, discrete and notebook GPUs and embedded. AMD needed competitive architectures to drive product sales and with Zen/Vega and future generations they should be able to do so.

 

[Ajay]

I know a physicist who works at GloFlo who implied that they have EUV systems coming in in 2017 for 7nm. He works on the manufacturing side @ Malta. I assume R&D already has at least one system. I don't really know if 7nm EUV will be ready for 2019 or not, but there is a significant effort going on there. One point about EUV, I would guess that it's only going to be used for the last two layers of SiXX (maybe even just one - if it's still too slow w/too much downtime).

 

[krumme]

Its pretty obvious mobiles is the driving force and funding the new nodes. Man 15 - 20 tapeouts this year on 7nm ! Euv a year later and 5nm so close.
It reminds me a bit of how quickly cameras improve in the phones. There is just an insane funding.

 

[krumme]

I guess this means 7nm phones 2018? And euv 7nm 2019? 5nm 2020? Crap...its incredible the phone market can still sustain that development.

Obviously its a huge advantage to share cost here. So even if amd dont get the first round its still breaking the hard depreciation.

 

[Lodix]

I guess this means 7nm phones 2018? And euv 7nm 2019? 5nm 2020? Crap...its incredible the phone market can still sustain that development.

Obviously its a huge advantage to share cost here. So even if amd dont get the first round its still breaking the hard depreciation.

This is "old" news alredy, this scheduling was confirmed last year

 

[dark zero]

And Intel is trying to shrink to that nm of density... Too bad that they came late to the party.

 

[krumme]

This is "old" news alredy, this scheduling was confirmed last year

Yes but before in history tsmc process nodes have been delayed. I can name a few . So the high number of actual tapeout in 7nm is a good sign. 15 to 20 - what is that? can you guys give a guess of the list?

 

[Doom2pro]

It's embarrassing how hard it is to product EUV light in sufficient quantities at this point... The over complicated methods being used currently would make any engineer cringe.

There are currently two techniques being used, one involves a convoluted method of dropping tiny balls of tin in a vacuum and precising hitting them with a 2kW CO2 laser which is the size of a school bus and is placed in the Subfab (Fab basement).

The other method requires a molten tin bath and a high capacity high voltage capacitor bank to create a high energy electrical discharge across the molten tin...

Either method is extremely inefficient, only produces around 200W max output power (production ready EUV will require as much as 400W or more) and loses as much as 80% of it's starting power through a convoluted vacuum path of mirrors and reflectors and is obviously insanely expensive due to the extreme complexity involved in it's design.

Ohh my Fin GOD... You might as well use an army of child laborers rubbing amber rods with cloths and billions of dollars worth of equipment to channel the resulting light to the work area... No wonder EUV is taking so long, nobody has stood up and provided a high power EUV light source capable of getting the job done.

I don't think there is another industry more desperately in need of some innovation, alternative ideas.

 

[oak8292]

Here is a link to the most recent rundown on the state of EUV and some information on the strategies of different companies.

http://semiengineering.com/why-euv-is-so-difficult/

Timing is everything. Every manufacturer has EUV equipment and is developing EUV processes. It is all about maturity and economics. It takes a couple of years to design a chip for a process. A process of record needs to be 'finalized' and somebody needs to place the bet that the equipment has the power and reliability to be 'economic' when the design is complete. If the roadmap on improvements is believable there may even be a company that takes a risk prior to the economics being 'perfect'. The spins are faster and yield could improve faster with EUV?

The die volume in mobile has definitely changed the landscape of Moore's Law. If Intel was the lone wolf in the industry with sub 20nm designs it seems unlikely that equipment vendors would be healthy and there would be even more 'optimizations' in the schedule. With TSMC and Samsung spending as much on Capex as Intel the 'innovation' pipeline for equipment is healthier. However, design costs are getting outrageous and unless designs get cheaper the price of entry is going to limit the number of players able to ante up.

 

[Lodix]

Yes but before in history tsmc process nodes have been delayed. I can name a few . So the high number of actual tapeout in 7nm is a good sign. 15 to 20 - what is that? can you guys give a guess of the list?

I guess it will be mostly SOCs for Mobile divices ( from: Nvidia, Apple, Huawei, Mediatek, Qualcomm?, Rockchip ) and high performance GPUs (Nvidia,AMD?). Maybe some hign end server processors...

 

[krumme]

......deleted.....

 

[Phynaz]

The latest status on EUV:
http://www.eetimes.com/document.asp?doc_id=1331252

 

[Ajay]

It's sure looking like EUV wasn't a good bet. Massively high output lasers for sub par W/cm2 wafer level output. Stunning slow progress .

 

[krumme]

As time goes and we get to smaller nodes euv becomes more economic viable. Right now the agreement is 250w output but at 5nm there really isnt a good and economic way to handle it without euv either. The cycle time will explode and impact even ttm seriously. Therefore we might see this output number lowered even if they cant get the last stretch to 250w. And we might have to settle for say 180w as one of the numbers in the article.

 

[Fanatical Meat]

Slightly off topic. How much longer can we realistically expect chips to shrink? Around what tiny size is it not practical to make them smaller? What happens next, I've heard quantum computing but I think we'll see different designs. Will we get to a point where chips won't change much for a long period of time?
Thoughts guys

 

[Qwertilot]

99% yes to the last point, the question is when Exponential increases in tech like chip people are still managing to maintain essentially can't be sustainable for ever. Sometime moderately soon though - you can tell that they're pushing the boundaries already from how small some of the increases are getting.

There will be other major advances once silicon shrinking runs out, but those will rely on really major fundamental breakthroughs and you simply can't rush those, especially not with having to get them produced on a budget for millions of chips at a time.....

Quantum computing may well do stuff, perhaps more likely to stay at least moderately specalised. Honestly, being objective, for most purposes even if chips stopped shrinking now we'd be doing very well.

 

[Phynaz]

Slightly off topic. How much longer can we realistically expect chips to shrink?

Can't be predicted because it comes down to what the materials guys can come up with.

 

[dullard]

Slightly off topic. How much longer can we realistically expect chips to shrink? Around what tiny size is it not practical to make them smaller? What happens next, I've heard quantum computing but I think we'll see different designs. Will we get to a point where chips won't change much for a long period of time?

For the last 45 years, we have averaged a 14%/year shrink in the node size (20% shrink every 18 months if you want it in Moore's law timespans). We don't get a shrink every year, but that average trend has kept pretty steady for decades. That trend is likely to end soon, but if it did not end then we would reach 1 nm in about 15 years. That is about as small as you can possibly make a wire (it is less than 4 copper atoms wide). I don't think it is practical to make electrically conducting materials much smaller than 1 nm as long as we need to use whole copper atoms. Even if we went with the smallest free-standing carbon nano tube, we would hit a barrier at 0.4 nm with those.

1 nm in 15 years is about the most rosy scenario you could have. There are many other constraints, so I suspect that we will hit a brick wall after about 5 nm that will slow the process way down (quantum tunneling for example, or even just trying to get heat out of such a small chip). 5 nm should be doable around year 2020 at best, but probably closer to 2022.

After that, instead of thinking about size, we can have other improvements. We could just use larger chips. They'd be more expensive, but processors could still get faster with more cores. Or we could have better arrangements of components. Or we could utilize three dimensions far more than we do (processors don't have to be mostly planar). Quantum computing is very fast for very specific tasks and terrible at the rest. We may need hybrids which are part standard processor and part quantum. Etc.

People will keep inventing ways of making better processors. It just comes down to cost and demand. The vast majority of people don't need faster processors than we have now. So, I suspect the customer demand to keep shrinking node sizes will diminish greatly at about the same time that we start to hit the brick wall of size of the nodes (~5 nm). Thus, that 5 nm might be the cost-prohibitive end to the pace that we have now.