A question on silicon wafers

[StrangerGuy]

We all know AMD and Intel enjoys showing off their finished wafers to the public right? Since those wafers are circular, and the CPU dies are orthogonal, those dies at the edges of the circle obviously need to be discarded...So why do they still waste materials on producing these useless imcomplete dies? There must be a good reason to do so right?

 

[TuxDave]

Beats me. I assume the cost of the wasted material is smaller than the cost of not printing a square when it actually could've fit.

 

[PottedMeat]

Hmm dunno. It seems like not exposing the partial dies would save time at the least. Anyone know about how long each layer is exposed?

 

[schenley101]

I believe that it is because they don't want to put any dies on the edge of the wafer for handling purposes.

 

[boardsportsrule]

the process of making dies has alot to do with layering chemicals onto the slab of silicon... a circle spins perfectly, and the chemicals will be an even layer over the whole circle...a square would be much harder to keep as steady...

just based on thinking, im no expert.

 

[boardsportsrule]

http://forums.anandtech.com/showthread.php?t=1720377

 

[TecHNooB]

I think it has to do with the process of making a VERY VERY pure silicon wafer. It's the equivalent of dipping a stick into honey and pulling it out.. a circle will form. This is from my very limited knowledge based on a course I took last semester The book was written in the 1950-60s.

 

[silverpig]

Wafers are circular by nature. The resists are spun on and I can tell you from experience that spinning resist onto a square gives you non-uniform thickness. After that you just expose the whole wafer in one shot so you don't lose any time or anything.

Basically, you use a circle because that's the wafer's shape and the optimal spinning shape. After that, everything that is done is done to the entire wafer so you don't lose anything by doing it this way.

 

[TuxDave]

Wafers are circular by nature. The resists are spun on and I can tell you from experience that spinning resist onto a square gives you non-uniform thickness. After that you just expose the whole wafer in one shot so you don't lose any time or anything.

Basically, you use a circle because that's the wafer's shape and the optimal spinning shape. After that, everything that is done is done to the entire wafer so you don't lose anything by doing it this way.

The question wasn't regarding why the wafers are circular. It's more of why do they do a litho mask pattern all the way to the edge. (resists I can understand why it just naturally covers the whole thing) I didn't think that the litho reticle covers the whole wafer but instead needs to step and repeat the pattern throughout the whole wafer including the far edges.

It could very well be that the reason they repeat it all the way to the edge is to ensure even density. Otherwise the outside dies may etch differently since they are neighboring nothing.

 

[Net]

Its the shape of the silicon ingot after the seed is pulled from the silicon melt.

search google using "making silicon ingot"

 

[PottedMeat]

It could very well be that the reason they repeat it all the way to the edge is to ensure even density. Otherwise the outside dies may etch differently since they are neighboring nothing.

yeah that sounds reasonable. spinning on resist at the edges bordering a blank die may have a different thickness than a die next to a die. more predictable density -> higher probability of good die -> more money!

 

[Juncar]

It just has to do with how they manufacture it. Things like molecular beam epitaxy and chemical vapour deposition is used to lay thin layer of pure crystalline layer like silicon oxide, and they can't really control where the particles will land so they just cover the entire wafer with it for even distribution. They can't control the movement of particles with perfect accuracy, which is why they apply the the process evenly across the entire wafer. It is much cheaper for them to do this than to invest in ultra precise machines that will produce dies only up to the square boundaries that fit the wafer.

 

[silverpig]

The question wasn't regarding why the wafers are circular. It's more of why do they do a litho mask pattern all the way to the edge. (resists I can understand why it just naturally covers the whole thing) I didn't think that the litho reticle covers the whole wafer but instead needs to step and repeat the pattern throughout the whole wafer including the far edges.

It could very well be that the reason they repeat it all the way to the edge is to ensure even density. Otherwise the outside dies may etch differently since they are neighboring nothing.

They just make the mask big enough to cover the entire thing.

You design a die in your cad program: #

You then copy and paste it until it fully covers the wafer

#######
#######
#######
#######
#######

You then write your mask, then use it in the lithography.

 

[CycloWizard]

Marangoni flows.

http://en.wikipedia.org/wiki/Marangoni_effect

 

[TuxDave]

They just make the mask big enough to cover the entire thing.

You design a die in your cad program: #

You then copy and paste it until it fully covers the wafer

#######
#######
#######
#######
#######

You then write your mask, then use it in the lithography.

Is that right? I haven't seen a modern mask so I didn't know if they had a mask large emough to expose the whole wafer at once. Guess that would remove the need for a precise stepping machine. Are you sure that's how it's done in the industry? I'm assuming that the mask image is magnified down to the wafer surface so that means the wafer mask needs to exceed 300mm.

 

[f95toli]

Is that right? I haven't seen a modern mask so I didn't know if they had a mask large emough to expose the whole wafer at once. Guess that would remove the need for a precise stepping machine. Are you sure that's how it's done in the industry? I'm assuming that the mask image is magnified down to the wafer surface so that means the wafer mask needs to exceed 300mm.

I don't know for sure how it is done in industry. But I would assume that at least some steps include straightforward photo-lithography (for patterning pads etc) which at least in principle can be done over a whole wafer at once.
Also, you don't HAVE to use the whole mask. When I design masks (this is for research) I usually just use a "square" area and leave the edges free, this makes it much easier to handle the mask and the finished wafers. You can also write useful bits of information, dicing marks etc outside of the main pattern.
That said the masks I use are quite a bit smaller than what is used in industry (I use 3" or 4" mask) so I am not sure how much of this applies to commercial production.

 

[TuxDave]

I don't know for sure how it is done in industry. But I would assume that at least some steps include straightforward photo-lithography (for patterning pads etc) which at least in principle can be done over a whole wafer at once.
Also, you don't HAVE to use the whole mask. When I design masks (this is for research) I usually just use a "square" area and leave the edges free, this makes it much easier to handle the mask and the finished wafers. You can also write useful bits of information, dicing marks etc outside of the main pattern.
That said the masks I use are quite a bit smaller than what is used in industry (I use 3" or 4" mask) so I am not sure how much of this applies to commercial production.

What wafer sizes and smallest feature size are you using for your research? (just for my curiousity sake).

 

[f95toli]

What wafer sizes and smallest feature size are you using for your research? (just for my curiousity sake).

It varies. Sometimes we quite litteraly fabricate single chips and they are either 5x5mm2 or 2.5x2.5xmm2; usually because we are using an expensive or rare substrates (say a good batch of GaAs with embedded 2DEG).

The masks are either 3" or 4", this tends to be the standard size for manual mask aligners. And since everything is done manually we can put several "layers" on the same mask.

Smallest feature size is about 2um for photolithography if we want to have good yield, everything smaller than that is usually done using direct write e-beam lithography (where we can go down to about 100-200nm, depending on the material).
The mask I am designing at the moment will probably use 3 layers for photolithography and 2 e-beam layers. so it is really simple compared to what you would use for e.g. a CPU. The mask is for a circuit that combines III-V semiconducting components with superconducting microwave circuitry.

 

[BEL6772]

Is that right? I haven't seen a modern mask so I didn't know if they had a mask large emough to expose the whole wafer at once. Guess that would remove the need for a precise stepping machine. Are you sure that's how it's done in the industry? I'm assuming that the mask image is magnified down to the wafer surface so that means the wafer mask needs to exceed 300mm.

No super-size masks. We use steppers to repeat the exposure over the surface of the wafer. A single mask will have multiple die on it, which is a large part of the reason we print over the edges of the wafers ... to print the ones near the edge that will be complete, we also print the ones on the same mask that will only partially land on the wafer.

The other consideration is that we need to keep the wafers flat. Polish, planar, and etch processes work at different rates on patterned vs un-patterned areas. We don't want topology issues that would result from un-patterned regions around the edge of the wafer.

 

[TuxDave]

No super-size masks. We use steppers to repeat the exposure over the surface of the wafer. A single mask will have multiple die on it, which is a large part of the reason we print over the edges of the wafers ... to print the ones near the edge that will be complete, we also print the ones on the same mask that will only partially land on the wafer.

The other consideration is that we need to keep the wafers flat. Polish, planar, and etch processes work at different rates on patterned vs un-patterned areas. We don't want topology issues that would result from un-patterned regions around the edge of the wafer.

Thanks for your input! That's what I last remembered that you had to use steppers to repeat an exposure on the wafer and not have some sort of jumbo mask. Good point on the mask containing multiple dies and so while an exposure may get cut off, a die may actually make it. That's something I didn't think of.

I can only think of a couple exceptions to where I think it might have been a single die to single mask. Gigantic stuff like Fermi or "something else" that's reaching the maximum reticle size.

 

[Brian Stirling]

One other reason that they print to the edge is that those "useless" die can be used for testing purposes so that even if the die is incomplete it can still be tested to monitor process uniformity etc.


Brian

 

[canis]

One other reason that they print to the edge is that those "useless" die can be used for testing purposes so that even if the die is incomplete it can still be tested to monitor process uniformity etc.


Brian

How are the useless die tested?

 

[Brian Stirling]

How are the useless die tested?

If you probe an individual transistor it doesn't matter if the die is complete.


Brian

 

[bigdog1218]

It's to ensure uniformity on the wafer throughout the entire process. If the edge has a different stack then the center of the wafer it will behave differently under certain processes. Just look at a process like RTP where wafers are heated to 1000C in seconds, if the edge of the wafer is heating at a much slower rate then the center, the wafer will break.

It's much easier to just cover the entire wafer with the same pattern and not worry if the edges will behave differently. Also, the only area that would actually save any time is Litho and it's not a huge amount of time, and the rest of the process cover the entire wafer so it wouldn't really save any materials.

 

[Eskimo]

The answer to the OP has already been provided by BEL6772. Judging from his location I can guess where he might work ;-) I'll answer a few more that were posed in this thread.

Are you sure that's how it's done in the industry? I'm assuming that the mask image is magnified down to the wafer surface so that means the wafer mask needs to exceed 300mm.

As was previously noted modern scanners can not image the entire wafer surface at once. Mainstream lithography tools from ASML, Nikon, and Canon all use 4x reduction masks measuring 6" square by 0.25" thick. The maximum allowable field size (area printed by one exposure) is 33mm x 26mm as printed on the die. ( 132mm x 104mm on the 6" mask)

Anyone know about how long each layer is exposed?

Modern scanners in production average between 100-150 300mm wafers per hour. Discounting wafer handling and alignment overhead that works out to about 30 seconds of exposure per wafer. A 300mm wafer will average around 80 exposure shots per layer including edge fields. CPU & Memory (NAND & DRAM) devices today are composed of between 20-35 layers depending on complexity and number of metal layers.