How is Nvidia planning to counter 256MB/512MB of stacked Infinity Cache on RDNA3?
It won't change anything much. If you look back at the slides AMD provided, the performance really tapered off after 128 MB for anything that wasn't 4K. It just means that a competing NVidia card doesn't gain as much as the resolutions increase like we see with current cards where AMD will win at 1080p but gets slightly overtaken at 1440p and is solidly behind in 4K.
For other workloads it doesn't matter much unless it lets some data set fit entirely in cache that otherwise couldn't. Otherwise the cache is larger, but there are more CUs to feed that are requesting data. For some workloads it comes out a wash.
Maybe that's the only way AMD knows how to increase raytracing performance.I do think Infinity Cache is L3, while this talk in regard to Lovelace is about L2. Surely there is advantage in that.
I think raytracing will benefit from it especially, and is the primary reason of the increase (if it happens).
It won't change anything much. If you look back at the slides AMD provided, the performance really tapered off after 128 MB for anything that wasn't 4K. It just means that a competing NVidia card doesn't gain as much as the resolutions increase like we see with current cards where AMD will win at 1080p but gets slightly overtaken at 1440p and is solidly behind in 4K.
For other workloads it doesn't matter much unless it lets some data set fit entirely in cache that otherwise couldn't. Otherwise the cache is larger, but there are more CUs to feed that are requesting data. For some workloads it comes out a wash.
They have a choice of keeping the same transistor count and gaining power efficiency or increasing transistor density at the expense of power consumption. They went with the latter approach.Something is strange with Hopper's Power consumption. 700W and going from N7 to N4. I was expecting a real efficient chip using N4, like 400W or less.
N4 > N5 > N7 in terms of power efficiency from process perspective.
I don't know if you fully thought about what you wrote.They have a choice of keeping the same transistor count and gaining power efficiency or increasing transistor density at the expense of power consumption. They went with the latter approach.
Die will be smaller so they profit more.If they keep same transistor count why bother to move to N4.
The higher density itself will increase the power draw.Newer full nodes means higher density and the tradeoff is between performance and efficiency. Keeping transistor efficiency same means higher performance.
I don't know if you fully thought about what you wrote.
If they keep same transistor count why bother to move to N4.
Newer full nodes means higher density and the tradeoff is between performance and efficiency. Keeping transistor efficiency same means higher performance.
But the almost 2x TDP means something else is up and it is not a process problem.
Die will be smaller so they profit more.
The higher density itself will increase the power draw.
Because the required voltage decreases (Less heat so cooler). But then they have to increase the voltage to keep the transistors stable at higher frequencies (more heat again!). It's a balancing act.Does not density increase as they move to smaller and smaller nodes? Why there is always expectation that those smaller nodes are going to be cooler?
I don't know if you fully thought about what you wrote.
If they keep same transistor count why bother to move to N4.
Newer full nodes means higher density and the tradeoff is between performance and efficiency. Keeping transistor efficiency same means higher performance.
Does not density increase as they move to smaller and smaller nodes? Why there is always expectation that those smaller nodes are going to be cooler?
Apples and Oranges comparison. AMD's cache hit rate issue was about the architecture, not anything related to caching itself. Improvements to the architecture will drastically improve the hit rate for IC. Nonetheless, as another user stated, this is L2 cache being discussed, not IC.
Agreed. I'd argue that the 2-4x increase in Infinity Cache is there more so to support 3x the compute units on the same sized memory bus rather plus any overhead required to coordinate two GCDs rather than an attempt to improve IPC. As you mentioned previously, even if you took a hypothetical 6900XT and slapped on twice the IF, the hit rate doesn't increase all that much and I suspect the performance won't either.But at some point you get diminishing returns. Look at Zen 3D which is fairly niche in terms of what applications will actually get an improvement from the extra cache. RDNA3 similarly isn't going to see a 2x improvement just from having 2x the Infinity Cache.
Agreed. I'd argue that the 2-4x increase in Infinity Cache is there more so to support 3x the compute units on the same sized memory bus rather plus any overhead required to coordinate two GCDs rather than an attempt to improve IPC. As you mentioned previously, even if you took a hypothetical 6900XT and slapped on twice the IF, the hit rate doesn't increase all that much and I suspect the performance won't either.
Edit- Speaking of which, looks like 600 watts is in; as is a 384bit bus with 24gb of ram for the highest end. Nothing surprising then. I'm a bit confused about the air cooling claims, was under the impression that topped out at 450 watts... unless the card is severely restricted to 450watts constant and might go up to 600 very temporarily.
Something is strange with Hopper's Power consumption. 700W and going from N7 to N4. I was expecting a real efficient chip using N4, like 400W or less.
N4 > N5 > N7 in terms of power efficiency from process perspective.