Question Alder Lake - Official Thread

[Hulk]

With the release of Alder Lake less than a week away and the "Lakes" thread having turned into a nightmare to navigate I thought it might be a good time to start a discussion thread solely for Alder Lake.

 

[TheELF]

Isn't that what the customer gets when they buy the product?

Customers also eat detergent pods, doesn't mean that reviewers should test those in that way.
Reviewers are not even telling people that you could be using a different setting or mobo with much less power usage and barely any performance reduction.
Also the customer only gets that if they buy the exact same mobo, other, even z, mobos could have lower maximums, and lower tier mobos definitely have lower settings, how many people that don't overclock bother with getting the hardcorest z overclocking mobo?

 

[Zucker2k]

That's where we are, Intel finally removed all the 14nm manure from their home and we're so grateful and happy with... a state of normalcy.

Is 14nm the donkey or the cow? I'll actually call it the goose that laid the golden eggs, with a plot twist.

Looking at how big GC is, on 10nm, Intel had no choice but to implement the hybrid system in order to save area first, followed by the added inherent benefits of GRMT, which they could tweak up to a satisfactory ipc level. The other issue to consider is per core power consumption at the frequencies required to compete with the 5950x. This definitely required a hybrid system. The 12400f, with its 4GHz all core clocks is positioned closer to the optimum v/f to not look too shabby in power consumption vs the 5600x. Those clocks won't allow the 12900k to shine vs 5950x, though power consumption would've certainly been noticeable, in a good way.

 

[DrMrLordX]

Customers also eat detergent pods

If that's the crux of your argument, you have no argument. Many users simply aren't going to go into the UEFI to tweak PL values, at all.

 

[TheELF]

Looking at how big GC is, on 10nm, Intel had no choice but to implement the hybrid system in order to save area first.

Actual die of 8+8+igpu is smaller than the 11900 and 10900k, they made the whole chip larger for some reason, maybe to have space for future growth.

The other issue to consider is per core power consumption at the frequencies required to compete with the 5950x. This definitely required a hybrid system.

All intel would have to do would be to put an embargo to reviewers and mobo makers on using power lifted settings, just like AMD does to hide their PBO numbers.
If intel used a max of 142W for tmp just as ryzen then both performance and power draw would be very close to each other, within 10%

 

[JoeRambo]

There was discussion earlier about just how Gracemont is so potent in Cinebench style workloads, and now there are latency/throughput tables for ADL-S, both big cores and small cores. ( @ instlatx64 ).

Remember the CB23 workload as characterized by ChipsAndCheese is non-vector FP + ALU + minor L3 footprint and mostly fits even in 512KB of L2. The limiting factors on Zen3 seemed to be ROB size, FP register file capacity and load/store queues.
So CB23 workload "bottleneck" can be imagined as chain FP + ALU instructions, with interdependence stuck in a ROB that is full most of the time, competing for register resources in capacity and L/S speed.

Gracemont is a CPU that is just built for this type of workload:

MASSIVE for atom core ROB of 256. Same as ZEN3 has, allows the CPU to extract instruction parallelism far in the future.
Rather fast L1 with 3 cycle load latency and okayish L2 with low latency, but obviously impacted by sharing it with other cores. 2 Load and 2 Store ports combined with fast caches help move data fast in those critical for CB caches

And the core is provided with huge execution resources for FP and ALU operations:

Two 128bit vector adds per cycle, same as Golden Cove and ZEN3
Latency is important to faster break dependency chains when same data is operated in turn
3 cycles for Gracement, same for ZEN3. Golden Cove seems to have advantage here at 2 cycles

And it is the same with FP multiplication, Gracemon can execute two 128bit vector multiplications per cycles, just like ZEN3 or Golden Cove, only latency is 1 cycle slower than ZEN3 ( but same as GC @ 4).

So for non-vector X64 code, that is generated using SSE2 instructions using 128 bit registers, Gracemont has very similar throughput as big boys. Things like AVX2 256bit instructions having half of big core throughput or FMA having high latency and low throughput are irrelevant if workload in question does not use them.

Then there is mythological question about the real amount of vector ALU operations Gracemont can do per cycle:

PXOR xmm,xmm => 5 per cycle is fine, due to zeroing idioms, big core seems to do 6
POR/PAND/PXOR xmm1,xmm2 => 3 per cycle matches Intel diagrams, matching big core

POR/PAND xmm,xmm ( same register ) operations => FOUR per cycle, even if according to Intel there are 3 vector ALUs ports.

So when Intel vector ALUs do not need to use more than 1 register from file, they can somehow execute more instructions than there are execution ports

Of course that means that Intel is bullshitting with diagrams and there are in fact more resources - true FP execution port configuration is not 3x128bits as we are led to believe, but likely 2 256 bit ports that are limited by FP register file ports and FADD/FMUL unit width of 128bits.
These units can be freely split into four 128bit ALU execution units and when faced with dual 256 ALU operations face minor penalty due to FP register file ports -> they can do 256bit ops ALU with throughput that is larger than half of 128bit.

The implications of this for the future are: Intel can easily unlock even more vector power on Gracemonts

 

[Hulk]

As a computer enthusiast I give Intel a lot of credit for Alder Lake. Zen 3 was a knock out blow to them. Not only did they get up off the canvas and respond, but they did so with gusto.

Alder Lake arrived with a new Golden Cove microarchitecture along with the new Gracemont microarchitecture in the first time ever hybrid x86 design. And to top all of this off it arrived on a new 10ESF (Intel 7) node. That's quite a bit of innovation all at once.

I was starting to think Intel was the new IBM and beginning a long slide. Now I'm hopeful.

 

[igor_kavinski]

Leaked Alder Lake Core i3 would be first interesting budget CPU in almost 2 years | Ars Technica

What is the point of that i3 without iGPU? Intel expects people to pair it up with a Geforce 710 or worse a 210, just to get a display output?

 

[Heartbreaker]

Only Apple fans, many of which are too young to remember the days of PPC, when Apple couldn’t keep up with anyone.

From where I sit, you were one of the most partisan posters.

 

[Heartbreaker]

As much as I've been deeply impressed with Zen3, I'm really happy that the pricing barrier for high performance parts is breaking open to a more mass market way. $200 12400 should equal the 5600X, and when $100ish B660 mobos arrive to pair with Gear1 DDR4, it will really mark a return to more sane pricing.

Yeah, B660 with DDR4 is definitely what I want to see. The budget end of the market needs more love.

The GPU market needs a year like this.

 

[TheELF]

Leaked Alder Lake Core i3 would be first interesting budget CPU in almost 2 years | Ars Technica

What is the point of that i3 without iGPU? Intel expects people to pair it up with a Geforce 710 or worse a 210, just to get a display output?

All skus will have F and non F models, would be weird if intel would change that now.
The model without an iGPU will be fine for people upgrading that already have a half way decent dGPU and of course OEMs that have the dg1 cards or a big stock of other crap dGPUs.

 

[hemedans]

Uh, beating Apple's ST performance within a 35W power budget is easy.

Beating Apple's MT performance within a 35W budget is the difficult one.

If wccftech leak is true, alderlake HK is better than M1 max in both single and multithread perfomance, lets wait for official numbers.

 

[DigDog]

No it cant, DDR4 and DDR5 memory/stick is not physically compatible.

View attachment 52072

it was a joke bruh

 

[lobz]

There was discussion earlier about just how Gracemont is so potent in Cinebench style workloads, and now there are latency/throughput tables for ADL-S, both big cores and small cores. ( @ instlatx64 ).

Remember the CB23 workload as characterized by ChipsAndCheese is non-vector FP + ALU + minor L3 footprint and mostly fits even in 512KB of L2. The limiting factors on Zen3 seemed to be ROB size, FP register file capacity and load/store queues.
So CB23 workload "bottleneck" can be imagined as chain FP + ALU instructions, with interdependence stuck in a ROB that is full most of the time, competing for register resources in capacity and L/S speed.

Gracemont is a CPU that is just built for this type of workload:

MASSIVE for atom core ROB of 256. Same as ZEN3 has, allows the CPU to extract instruction parallelism far in the future.
Rather fast L1 with 3 cycle load latency and okayish L2 with low latency, but obviously impacted by sharing it with other cores. 2 Load and 2 Store ports combined with fast caches help move data fast in those critical for CB caches

And the core is provided with huge execution resources for FP and ALU operations:

Two 128bit vector adds per cycle, same as Golden Cove and ZEN3
Latency is important to faster break dependency chains when same data is operated in turn
3 cycles for Gracement, same for ZEN3. Golden Cove seems to have advantage here at 2 cycles

And it is the same with FP multiplication, Gracemon can execute two 128bit vector multiplications per cycles, just like ZEN3 or Golden Cove, only latency is 1 cycle slower than ZEN3 ( but same as GC @ 4).

So for non-vector X64 code, that is generated using SSE2 instructions using 128 bit registers, Gracemont has very similar throughput as big boys. Things like AVX2 256bit instructions having half of big core throughput or FMA having high latency and low throughput are irrelevant if workload in question does not use them.

Then there is mythological question about the real amount of vector ALU operations Gracemont can do per cycle:

PXOR xmm,xmm => 5 per cycle is fine, due to zeroing idioms, big core seems to do 6
POR/PAND/PXOR xmm1,xmm2 => 3 per cycle matches Intel diagrams, matching big core

POR/PAND xmm,xmm ( same register ) operations => FOUR per cycle, even if according to Intel there are 3 vector ALUs ports.

So when Intel vector ALUs do not need to use more than 1 register from file, they can somehow execute more instructions than there are execution ports

Of course that means that Intel is bullshitting with diagrams and there are in fact more resources - true FP execution port configuration is not 3x128bits as we are led to believe, but likely 2 256 bit ports that are limited by FP register file ports and FADD/FMUL unit width of 128bits.
These units can be freely split into four 128bit ALU execution units and when faced with dual 256 ALU operations face minor penalty due to FP register file ports -> they can do 256bit ops ALU with throughput that is larger than half of 128bit.

The implications of this for the future are: Intel can easily unlock even more vector power on Gracemonts

Very nice post, man!

 

[uzzi38]

If wccftech leak is true, alderlake HK is better than M1 max in both single and multithread perfomance, lets wait for official numbers.

I have no doubt it will be.

But like I said, the difficult thing would be beating Apple on MT at that given power budget, not beating Apple full-stop. I have no concerns about ADL-P beating M1 Max given enough power (judging by those early numbers I'd bet around 50W)

 

[semiman]

What I'm enjoying the most is the dichotomy of praising the new hybrid architecture while acknowledging that the classic setup on the 6+0 chips will be the one to bring that awesome perf/dollar ratio.

It's almost as if it wasn't the innovation behind hybrids we we missing, but simply a decent architecture on a competitive node. Reminds me of a joke about a man who is feeling depressed due to his poor social status, with a very crowded and noisy home. The village elder advises him to move his cow in the home as well, then his donkey, then his chickens. The man obviously becomes increasingly stressed, to the point of desperation. Then the elder tells him to progressively remove the chickens, donkey, and finally the cow. The man can barely contain his feelings of happiness and gratitude for his newfound life.

That's where we are, Intel finally removed all the 14nm manure from their home and we're so grateful and happy with... a state of normalcy.

Actually, that's true for many people who don't really care about performance per power. Intel's hybrid architecture came to defend against future AMD's strike using Zen 4 while keeping low power efficiency in a laptop segment.

Intel desperately needs high MT uplift next year, because Zen 4 will be out with TSMC N5(+high IPC boost). This will result in a complete disaster if no Monts are available. 10ESF(Intel 7) coves(+without tiled architecture) are no match for Zen 4 chiplets. Intel can get +25% ~ish MT uplift simply by adding 2 Gracemont cores while keeping ST leadership by optimizing Golden Cove(a.k.a. Raptor Cove). The ecosystem needs to be ready before then so Alder lake is here now. They'll struggle, but at least they can manage. Of course, real problem happens in server though. Rapids core count is not enough yet. Lucky for Intel, currently TSMC N3 is in trouble so there will be less capacity in N5(+N4) for AMD.

Meanwhile, In a mobile segment, Alder Lake P and Raptor Lake P can provide obvious power saving even against Zen 4 APUs due to nature of small core. It's already proven in smartphones.

After that, hybrids will defend x86 against ARM attacks from IDC edges and cloud providers. It might not work, or too late. But better try than doing nothing. AMD's cut-off approaches might not be enough to repel a horde of ARM cores.

 

[eek2121]

As a computer enthusiast I give Intel a lot of credit for Alder Lake. Zen 3 was a knock out blow to them. Not only did they get up off the canvas and respond, but they did so with gusto.

Alder Lake arrived with a new Golden Cove microarchitecture along with the new Gracemont microarchitecture in the first time ever hybrid x86 design. And to top all of this off it arrived on a new 10ESF (Intel 7) node. That's quite a bit of innovation all at once.

I was starting to think Intel was the new IBM and beginning a long slide. Now I'm hopeful.

We will see what AMD cooks up for Zen3D.

From where I sit, you were one of the most partisan posters.

Wrong, but rather than argue, If you have nothing useful to contribute, the exit doors are above you and below you.

 

[Mopetar]

We already have some information from AMD themselves on Zen 3D performance and can draw a reasonable idea of what best case performance looks like.

 

[Roland00Address]

Lol. "Arbitrary Standard" should be the official trademark of Apple.

And forget 2020 Apple performance, given that the newest M1 derivatives still lag in peak ST performance to these releases.

Edit : Oh no, I've angered an Apple fan 😂😂 The downvote, so devastating 🤣🤣

Hilarious, and revealing at the same time.

It is an arbitrary standard. People are going to buy windows machines that are 60%, 80%, 90%, 100%, or 120%+ the performance of a M1.

You are not going to get a gold star if the device is 103% the performance of a M1 in single thread, instead of 91%. Carrying about that threshold feels like pride and vanity to me.

I am not a macOS user. I like super cheap hardware, like $200 to $480 cheap (but closer to $400 than $480) 😛

 

[blckgrffn]

It is an arbitrary standard. People are going to buy windows machines that are 60%, 80%, 90%, 100%, or 120%+ the performance of a M1.

You are not going to get a gold star if the device is 103% the performance of a M1 in single thread, instead of 91%. Carrying about that threshold feels like pride and vanity to me.

I am not a macOS user. I like super cheap hardware, like $200 to $480 cheap (but closer to $400 than $480) 😛

We don't get a piece of flair to pin to our lapels for getting M1 performance from a non-Apple piece of hardware, whenever it shows up? Are you sure? How will everyone know how smart and value driven we are?

/S

I am not buying a Mac because I am Windows across all my things right now and I put a premium on having my tools be homogenous, but I am looking forward to getting something better than my 8th Gen i7 in a laptop and picking up some decent battery life too. It's not like it's too slow, really, but I am wanting something new and shiny and preferably without two GPUs (I don't like how hybrid stuff makes it hard to know what is going on or makes you choose performance vs battery life). Xe or RDNA2 in a Lenovo Thinkpad is how I will be rolling, no matter how shiny that M1 Air might be

Given how OEM relationships are working and how AMD is maybe (correctly, as a stockholder, imo) keeping their best for the datacenter it's looking like an Intel part right now. So lets go, Intel!

 

[AdamK47]

I contemplated creating an "Alder Lake - Builders Thread" to get those with the hardware talking about experiences with it. Ultimately passed on it knowing there would be undesirable (to put it politely) bleed over from this thread.

 

[jpiniero]

I contemplated creating an "Alder Lake - Builders Thread" to get those with the hardware talking about experiences with it. Ultimately passed on it knowing there would be undesirable (to put it politely) bleed over from this thread.

For the best I guess. Hardware Unboxed had a video suggesting Alder Lake's sales have been bad. Normally I would be skeptical cuz Youtubers but from what I'm seeing that looks correct. Only the i9 seems to have any demand and it's basically OOS.

 

[Zucker2k]

For the best I guess. Hardware Unboxed had a video suggesting Alder Lake's sales have been bad. Normally I would be skeptical cuz Youtubers but from what I'm seeing that looks correct. Only the i9 seems to have any demand and it's basically OOS.

I'm not sure if you're joking. If reddit is any indication, the only thing holding most people up from their builds are LGA 1700 retention kits and compatible coolers, and DDR5 stock. Those who went ahead and bought DDR5 already are up and running. An impatient bunch have turned to DDR4, and some are also playing the waiting game to see if there are going to be any bugs while weighing whether to go DDR4 or DDR5.

 

[maddie]

I'm not sure if you're joking. If reddit is any indication, the only thing holding most people up from their builds are LGA 1700 retention kits and compatible coolers, and DDR5 stock. Those who went ahead and bought DDR5 already are up and running. An impatient bunch have turned to DDR4, and some are also playing the waiting game to see if there are going to be any bugs while weighing whether to go DDR4 or DDR5.

Using this as part of your argument against "sales are bad" doesn't really help.

 

[epsilon84]

I'm pretty sure DDR5 and Z690 mobo pricing is a big reason for the lacklustre sales figures.

It's the main reason why I haven't upgraded. I'm aware I can re-use my DDR4 without *too* much performance loss, especially when compared to lower end DDR5 kits. Ultimately we all know that DDR4 is just a stopgap measure for this platform, moving forward DDR5 is where the performance will be.

I'm also waiting to see how AMD responds with Zen 3D before I make my final upgrade decision.

 

[DAPUNISHER]

I contemplated creating an "Alder Lake - Builders Thread" to get those with the hardware talking about experiences with it. Ultimately passed on it knowing there would be undesirable (to put it politely) bleed over from this thread.

Do it Adam. Don't be daunted by any of that nonsense. If they start to off topic the build thread, report them, and it will get handled. Builder threads are not for versus flame wars, they are for help and advice.