With the release of Alder Lake less than a week away and the "Lakes" thread having turned into a nightmare to navigate I thought it might be a good time to start a discussion thread solely for Alder Lake.
They don't want us plebs having the "cool tech", like ECC, Optane NVDIMMS, etc. So typical.In addition to not validating it, I think they want to actively discourage AVX-512 use in the consumer space
I don't even think it's that. I think they pushed too far with AVX-512, and don't have any plans to support it on consumer hardware any time in the foreseeable future.They don't want us plebs having the "cool tech", like ECC, Optane NVDIMMS, etc. So typical.
Intel and other x86/x64 chipmakers really need some ammo to use against ARM in the consumer space, though.I don't even think it's that. I think they pushed too far with AVX-512, and don't have any plans to support it on consumer hardware any time in the foreseeable future.
Sure, but I don't think AVX-512 is that. Too niche, and too expensive. Plus, SVE being vector length agnostic (mostly) is definitely in its favor. Maybe time to go back to the drawing board.Intel and other x86/x64 chipmakers really need some ammo to use against ARM in the consumer space, though.
This. I wonder what the odds are that x86-family chips would adopt SVE? Is that even possible, legally-speaking?Plus, SVE being vector length agnostic (mostly) is definitely in its favor.
I suppose it's theoretically possible to license it, but in practice, I doubt it's a realistic possibility.This. I wonder what the odds are that x86-family chips would adopt SVE? Is that even possible, legally-speaking?
The efficient Gracemont cores cannot handle AVX-512 code. Adding AVX-512 would probably make the efficient cores lose their efficiency. Intel currently does not have a method to send AVX-512 code solely to the Golden Cove cores if the efficient Gracemont cores are enabled. So, any AVX-512 code could be scheduled to the Gracemont cores and crash. Until they fix that limitation, it is easier to just disable it and let the users who actually need AVX-512 enable it through the BIOS.Outside of "being evil", why would Intel disable AVX-512 on Alder Lake? Is there a QC issue?
They don't want us plebs having the "cool tech", like ECC, Optane NVDIMMS, etc. So typical.
I don't even think it's that. I think they pushed too far with AVX-512, and don't have any plans to support it on consumer hardware any time in the foreseeable future.
Adding AVX-512 would probably make the efficient cores lose their efficiency.
It's not something that currently has any significant value in the consumer space, while clearly imposing a significant cost. Shrinks may improve the cost aspect somewhat, but they don't do anything for its value proposition.Pretty sure doubling vectors are something that new process technology with improved perf/watt affords and ever since they stopped advancing on it, so did the increase in vector width. Because I know few years ago Intel was hinting of even wider vectors.
Kinda funny that you mention that. The big revelation with Ice Lake is that the primary real-world use for AVX-512 is wide loads and stores, which don't require much (if any) impact to clock speed. Merely splitting AVX ops into crude designations based on their compute penalty was enough to blunt most of the damage, but they went even further with Golden Cove. They introduced an entire microcontroller and associated code with the primary goal of handling AVX power behavior. SPR's probably going to do pretty well in that regard, for whatever good it does them.Icelake significantly improves on the clock throttling aspect when it comes to AVX-512, but it's also on 10nm. Coincidence? I don't think so.
I wouldn't be surprised that it is related to a security issue that we will hear about later when the bios changes are ready.
Not sure how intel thought that adding incompatible cores in the CPU to do the same thing wouldn't lead to issues,
Intel Reportedly Kills AVX-512 on Alder Lake CPUs
The end is near for AVX-512 on Alder Lakewww.tomshardware.com
Is this moving forward or retroactively? How does this work exactly?
The Intel RM1 is obviously quite noisy, as expected for any 3000+rpm fan.
Intel stock cooler for Alder Lake-S CPUs tested, up to 73°C with Core i5-12400 CPU - VideoCardz.com
Intel RM1 Stock Cooler for LGA1700 CPUs The first review of the Intel stock cooler appears online. The long-awaited refresh of the Intel stock coolers is coming with the 12th Gen Core 65W CPU series now set to launch in early January. Intel will be releasing three new stock coolers for Core i7...videocardz.com
They don't want us plebs having the "cool tech", like ECC, Optane NVDIMMS, etc. So typical.
VNNI has a couple of real world uses, but the problem is that it's shoehorned into the AVX-512 spec without fundamentally requiring 512b vectors. I think it would make a lot of sense to backport some of the functionality added with AVX-512 to 256b or smaller extensions that Atom could more easily absorb. But that would be yet more churn on the software side.You missed Ice Lake having AVX-512 all the way down to the -U models, including the i3-1000g1 and maybe the pentium 6805 (can't find the spec sheet for it to see if its disabled).
The main issue with consumer level AVX-512 from Intel, at least for Ice Lake U, tiger Lake, and Rocket Lake, is the fact that there is only one AVX-512 unit per core, limiting them to half the throughput that server has. With that limitation, it is rarely (though not always) faster than the same code implemented in AVX2. I see it in science tasks where someone will jave a go at hand optimizing code for maximum avx-512 usage and, while it absolutely flies on server hardware, it isn't any better, or maybe worse, on consumer chips with the same code, than previous versions in avx2 or something else.
It is at best a validation tool, a side show curiosity, or is so situational, that it's otherwise useless on the consumer side, at least up to Rocket Lake.
Oh, nice. Step in the right direction. Though I don't believe all of the new AVX-512 functionality (beyond the vector width itself) has similarly backported. Probably still some work to do there.
At one time, Holley zeroed in on NSP's 'scheduler', in essence an electronic traffic cop that keeps the many tasks a computer must perform running in harmony so things get done when they are supposed to. Though most computers have only one scheduler included with their operating systems, NSP would have added a second scheduler -- one "with unknown and untested implications," Microsoft executives wrote.
"Windows itself has a task scheduler, is that not true?" Holley asked.
"That's correct," McGeady said.
So didn't that mean the schedulers were redundant? Holley asked. No, McGeady said, since Intel's scheduler coordinated audio, video and other tasks that weren't handled by Windows in the same way.
"But they were both schedulers, weren't they?" Holley asked.
"We're using a term of art in computer science I'm not sure you understand," McGeady said.
But wasn't that scheduler "unknown and untested?" Holley asked.
"They were known and tested by us," the Intel executive said simply.
How so?! According to the article the previous schedulers would have reduced sales of newer windows versions while the new thread director helps with selling the newest windows OS.Reading that, it seems like a miracle that Microsoft co-operated with Intel for Alder Lake's Thread Director.
"I think there was serious and heartfelt concern that [computer makers] would pick up NSP and ship it with Windows 3.11 and use that as an excuse not to ship Windows 95," he told the court.
Not sure about that. It helps Intel sell Alder Lake. How does Microsoft benefit? AMD doesn't have similar hardware scheduling (yet) but their CPUs can still run Windows 11 fine. Microsoft may get performance/battery gains in their Alder Lake Surface hardware through this partnership though.How so?! According to the article the previous schedulers would have reduced sales of newer windows versions while the new thread director helps with selling the newest windows OS.