With the release of Alder Lake less than a week away and the "Lakes" thread having turned into a nightmare to navigate I thought it might be a good time to start a discussion thread solely for Alder Lake.
Intel sells the ecores in the way shown in these pictures.
Compared to a CPU without ecores it allows your foreground app to keep running at full speed while giving the background app a specified amount of compute that's always available to it, depending on the amount of e-cores.
The way you would keep your foreground app running at full speed on a CPU without e-cores would be to run the foreground app at real-time priority and the background app at idle priority meaning that the background app might never get any CPU cycles.
This is NOT mitigating potential responsiveness problems caused by the presence of E-cores, this is your foreground app getting the use of the full CPU (compared to a CPU without e-cores) meaning there is no slowdowns.
The wide variety of tests ensures that everyone can look up what matters to them
Phoronix have their test suite and that's it, whatever takeaways you make from that test suite should factor in the tests in that test suite. That's it.
Exactly, though the geometric mean posted at the end of the test suite is pretty useless unless your workload mimics the test suite almost exactly.
You have to realize that this is not being done for best performance or for best efficiency.These slides are interesting and as usual it's a rabbit hole when you start to analyze them because so much of the testing procedures is left out. Specifically the length of the test scripts.
I'm sure it doesn't work well all the time yet, but the theory is that TD will actively allow all cores to work on a task or boot a low importance thread from a P core to run something new that is more important.The fix seems so simple I must be wrong in my thinking. Simply keep the P's assigned to the foreground task but ALSO allow them to work on background tasks while keeping the foreground task as the priority. So if you are editing a photo and need the P's for 5 seconds to process a filter on a photo they would immediately move to the foreground app, process the filter, and then move back to the background apps until the foreground app needed them again.
You have to realize that this is not being done for best performance or for best efficiency.
This is purely a Apple thing of providing the best user experience, it's about the noob streamer not losing FPS or dropping frames on the recording without having to do anything special, and it's about the noob content creator not having to wait any longer importing and exporting pics while converting their video.
Not feeling your system ever being bogged down is far more important than actual performance and if actual performance is still pretty high it's a win win.
I'm sure it doesn't work well all the time yet, but the theory is that TD will actively allow all cores to work on a task or boot a low importance thread from a P core to run something new that is more important.
So basically what you are saying and more, I just have the suspicion that all apps and threads have to be running on the same priority for this to work correctly but I might be wrong.
Here is the difference between the previous pics which were targeted to noobs and what TD actually is supposed to do.
No matter how much work Intel puts into it, it won't be enough. That is because Windows can just override the Thread Director at its whimsy. The right solution is the a very long-term solution: recompile the software to properly place code on the right cores. By the time that happens, Intel would have gotten away from possibly the worst possible combination that you have (8 P and 4 E cores while trying to do something in both the background and the foreground).I remember watching that video when it came out and being excited to see it in action. Unfortunately in practice it's not working the way she explains it. P cores will "spin" and do nothing while you browse the web even if the E cores are compressing video in Handbrake in the background.
As far as I can tell NONE of that stuff they are talking about with the TD is happening. I'm going to have a little fun with this now. It's more like, "We at Intel have decided to put the foreground application on the P cores because we need the highest possible benchmark scores. We then cleverly shove all of the background tasks on the E cores. Kind of like sweeping dirt under the rug but in a modern way. See, we're Intel and we make old new again!"
The most ironic part of this is that the time and money spent on that video could probably have been used to actually fix the thread director instead of advertising it.
No matter how much work Intel puts into it, it won't be enough. That is because Windows can just override the Thread Director at its whimsy. The right solution is the a very long-term solution: recompile the software to properly place code on the right cores. By the time that happens, Intel would have gotten away from possibly the worst possible combination that you have (8 P and 4 E cores while trying to do something in both the background and the foreground).
But that would mean that TD director is working at least in this workflow of running a heavy workload together with background stuff.As far as I can tell NONE of that stuff they are talking about with the TD is happening. I'm going to have a little fun with this now. It's more like, "We at Intel have decided to put the foreground application on the P cores because we need the highest possible benchmark scores. We then cleverly shove all of the background tasks on the E cores. Kind of like sweeping dirt under the rug but in a modern way. See, we're Intel and we make old new again!"
But that would mean that TD director is working at least in this workflow of running a heavy workload together with background stuff.
In summary:
In terms of energy efficiency at similar clocks, Zen 2 cores are excellent. Golden Cove has to drop below 2 GHz to finish the encode job with the same energy budget as desktop Zen 2. Gracemont can do better, but also has to clock below 2 GHz. Again, we see desktop Zen 2 cores failing to gain efficiency at lower clock speeds. Their energy efficiency peaks when boost is turned off, and going lower actually makes the cores pull more total power. Renoir is much better at scaling down to low power. At least in the near future, AMD can probably get by without maintaining separate E-Core and P-Core architectures. They’re already covering both bases by changing L3 size and optimizing the same architecture for different power and performance targets.
- Out of the box, the 12700K prioritizes absolute performance over power efficiency. “Race to sleep” is complete bullshit, at least until you get down to very low power levels.
- Golden Cove is very efficient below 4 GHz, especially with a vectorized workload
- Even though it’s paired with E-Cores, Golden Cove still scales well to very low power levels.
- Gracemont is very efficient with integer workloads in the low 3 GHz range.
- 256-bit instructions give Gracemont a hard time. With libx264, it needs to go below 3 GHz before it really shines in terms of energy efficiency
- When run at sane clocks, both Alder Lake architectures show significant efficiency gains compared to Skylake
Chips And Cheese always goes into a lot of detail with tons of graphs. If you haven't browsed that website, the analyses are really well done. But the website itself is a nightmare to navigate or find anything. Thanks for this link.https://chipsandcheese.com/2022/01/28/alder-lakes-power-efficiency-a-complicated-picture/
A bunch of cool plots. Really great analysis overall.
Pretty much the same with all CPU review benchmark suites.
Something is fishy in this article. Looks like sponsored one.https://chipsandcheese.com/2022/01/28/alder-lakes-power-efficiency-a-complicated-picture/
A bunch of cool plots. Really great analysis overall.
Huh? The comparisons to Zen 2 are already extremely favourable, idk what on earth you're talking about. Especially when Renoir gets added into the mix there, the power efficiency advantage is clear.Something is fishy in this article. Looks like sponsored one.
They compare new and shiny Intel architecture to almost 3 years old AMD Zen 2. Time isn't standing still and AMD won't wait for intel to catch up.
I bet that comparison with Zen 3 doesn't look so good from efficiency perspective. At least they didn't include FX 9590 in the graphs ;-)
Sorry for my ignorance but easier how? He didn't have Zen 3 on hand or is there some other reason?The only reason why Zen 3 wasn't tested is that it was easier for Clam to test on Zen 2. That's it.
Yeah I don't think Clam does have one on hand. I know Cheese has a 5950X, but I don't think Clam does - I'm pretty sure the 3950X used for the review is Clam's desktop.Sorry for my ignorance but easier how? He didn't have Zen 3 on hand or is there some other reason?
Redfire on Twitter: "High resolution Alder Lake-S Die Shot: I believe this was sent to reviewers and it was on embargo till today. I'm not 100% sure. Resolution: 6950x3514 Link: https://t.co/7SKmi7f94F https://t.co/FTp3qvVjgI" / Twitter
Hope someone will label the different areas in the high resolution die shot.
Alder Lake P Die anotation(i7 H Laptop)
Alder Lake S Die Anotation(Desktop i9)
You didn't mention your country.Nice but I can only find ~150€ B660 MoBos...