What? The Chiplets are less than half the size of 14nm Zen dies, as expected... What were you expecting? Rice grains?
I have a hunch the one we're seeing is for EPYC only. We'll either see a different die for consumer (and/or Threadripper), or a substantially different I/O chip. Seems like people are expecting a very large L4 cache in that I/O chip, and I don't see them putting that in consumer stuff.
It'll definitely be interesting to see how things go.
That has nothing to do with the size of each CCX.
Top Rome 64 cores. 8x 8 core = 64. There are 8 chiplets. That's what 8x is. They literally said it in the livestream. You can see in the photos too.
There clearly are 8 chiplets in there. Nobody could've guessed that layout, though.
8 cores per chiplet, then. 2x4c CCX or 1x8c CCX, we'll see.
If that's still LGA4094/SP3/TR4, that controller die is surprisingly huge yet dirt cheap since it's built on 14nm.
Knowing AMD, it'll probably be the same chiplet design with a cut-down system controller.
With minimal IO you'd expect the chiplets to be minuscule.
Top Rome 64 cores. 8x 8 core = 64. There are 8 chiplets. That's what 8x is. They literally said it in the livestream. You can see in the photos too.
Yes, that is what I am suggesting .So you are suggesting Desktop Zen 2 will be 16 core (2x 8core CCX)?
I wouldn't be surprised, 7nm 8 core Zen would be tiny (Less than half 14/12nm Zen die size).
So you are suggesting Desktop Zen 2 will be 16 core (2x 8core CCX)?
I wouldn't be surprised, 7nm 8 core Zen would be tiny (Less than half 14/12nm Zen die size).
You may still have either 1 or 2 CCXes in each chiplet.
Currently on Epyc(1) we have 4x8 core = 32, with 8 cores per chip, 2 CCX per Chip and 4 cores per CCX.
We have no way of knowing if each chiplets has 2 CCX with 4 cores like current chips or they are moving to an 8 core CCX.
Personally I believe in an 8 core CCX, but it is a guess since there are no solid public information.
Knowing AMD, it'll probably be the same chiplet design with a cut-down system controller.
Ok, lets apply a bit of common sense to the 4x vs 8x cores per chiplet.
Q: If it were 4 cores per chiplet, where would the communication occur? (at a level where it would actually bother us)
A: At the Input/Output Controller (IOC). Which would mean double traces from CCX to IOC. Given the issues already present in routing around the IOC - its clearly logical that AMD stray away from that path.
If the communication occurs at the L3 within the chiplet, are we bothered? The L3 latency will be <20 cycles now that it is not running at MEMCLK.
I'm leaning towards 2x CCX per chiplet.
You mean 4 or 8 core CCX? Because Obviously there are 8 cores/chiplet.
You mean 4 or 8 core CCX? Because Obviously there are 8 cores/chiplet.
Yes 8 core chiplets, but we still don´t know if there is 8 cores single CCX per die or 2 CCX/4cores per die
I would bet on the same CCX arrangement as before. There really isn't a huge need to change.
Maybe I missed it but did they say where the I/O controller, 14nm, would be made? Could this be a way to burn off the required usage at GFs? Then when 7nm is more mature/cheaper they can switch to a updated 7nm controller. That alone will probably allow them to mature the controller and shrink it down for Zen3.
It's really odd how close the chiplets are. If it were for thermal reasons only they'd surely be further apart?
Perhaps they are all on something like a tiny interposer, to unify latency to the IO chiplet and have faster direct access between pairs of chiplets