I don't think we'll even see R3 7nm products. At least for a very long time. 4c/8t 7nm will clearly be R5. If yields are so bad or numbers of chiplets so huge, then maybe they harvest some ≤ 3c to stockpile and eventually put out a R3, if we're lucky.
Most R3 are RR and PR. 12nm/14nm is very long lived and cost effective to make transistors.
Their 12nm is still the bread and butter node for PC and mobile until then. I'm waiting to see what 12nm APU they come out with soon.
Where do you think the smaller IO Hub, GPU, Chiplets come from? The chiplet fairy? They need masks/designs too.
The problem is some people see a neat solution for a specific problem space, and quickly leap to thinking that it's the best solution for ALL problem spaces. It isn't.
For large number of CCX's the central IO hub (even if on another die) may be good for latencies. When they launch 7nm Epyc we find out. I hope soon.
They may go monolithic, but maybe every other generation, so they probably wait for at least Navi and likely longer, and go 7nm monolithic with Zen3.
There's a big difference between dollar volume and unit volume for ultra premium bleeding edge. It's okay for unit production costs to be higher if they really are limited edition high margin products, especially with yet another generation update Zen3 not being so far out in the future.