So bummed there is no new performance parts. Planning on upgrading in the spring and was hoping to keep an AMD CPU. But the current FX chips are not enough of an upgrade over what I have now.
Lower TDPs, 1 and 2 module I assume. Since they are now in the Celeron/Pentium/i3 area. Leaving i5 and i7 alone in the performance and enthusiast segments.In 2015, 'Carrizo' APUs will be launched to succeed Kaveri in the desktop market, featuring the Excavator architecture at two TDPs: 45W and 65W.
An example on how far from the goalpost AMD ended with Kaveri:
http://semiaccurate.com/2013/11/12/amd-misses-expectations-kaveri/
good research.
That just shows that its the process that is going to make or break Kaveri. I have a feeling that the process is what delayed Kaveri.
AMD's recent strategy has been to add performance as the process matures. So maybe we'll see that 1 gflop Kaveri in a year and with a new name.
So it's an objective fact that CMT is "crap"? And I haven't "missed" anything, it's the same old garbage; topic gets created about "something" and it's really just a poorly-veiled front to turn the topic into a AMD/Bulldozer sucks thread. Funny how out of the countless tech forums I've been on, it seems to happen the most here. Now that you guys get called out on derailing, you resort to the classic "you guys are just defending the company/being one-sided" cop-out. Try again!
We will have to wait and see if that confidence has any merit.Jim Keller said:"AMD are on track to catch up on high performance cores"*
AMD doesn't have the resources to do a ground up redesign of say the Thurban architecture (plus what they've learned from BD) and come out with a new more efficient multicore microprocessor.
CMT, objectively, doesn't scale well if it has to serve diverse workloads...
It's Excavator.DT claims this is SR die(or better to say part of the die shot). They got it from Extremetech who supposedly got it from AMD. Very fishy.
September 1st, 2010It's Excavator.
I've allways thought of SMT as the bastard child and here is why. Suppose you have one core. Now you SMT enable it. That means that you get to tap into that ~20% unused resources of the core if you just so happen to have another thread lying around that fits the bill.. and that bill really has to fit, dont it?
I like my hyperthreading, its a little something extra extra here and there, it is spice, but thats it.
From an coding angle and the operation system.... this must be a nightmare, I got these 4 real cores and then these 'maybe' 20% threads .. and if I put the wrong things (ie. fitting the bill) in these 20% threads the real cores/threads begins to suffer as well. We'll need some pretty smart AI to guide those schedulars soon.
I was thinking about general-purpose cores which scale from client to server across a wide range of workloads, sorry, should have made that clearer. Even so, only Silvermont and Quark don't have SMT. Quark is obvious, and Silvermont couldn't benefit much from SMT as long as the out-of-order engine can achieve high utilization, which seems probable in a 2-issue design. If there are only a few unused execution slots, implementing SMT doesn't make sense.SMT sure does have tradeoffs in 'CPU core quality' or else Intel would use it for every and all of their processors. It's obvious by Intels own product releases that SMT is an improvement only to a specific set of conditions.
True, but AFAIK nobody has used CMT in a high-performance CPU. Seems to indicate that it isn't regarded as useful for producing competitive products.Also, I doubt that there is much if anything stopping Intel to switch between SMT and CMT, or use a combination/drop it. As long as it is the most favorable improvement to whatever uarch they develop, of course. The same holds true for AMD.
ILP scaling gets slower but seems to be doing well, see Power8 and Haswell. It may be quite some time before it drops as dead as frequency scaling seems to have done. And even when ILP improvements stop, CMT isn't an obvious solution; just stack more of your CMT cores on a die, this also gives more threads but should be easier to balance for an optimum of ILP/integer/FP/die area/power use.Dunno. Current pipelines have gotten quite fat and ILP scaling seems to be limited. CMT really isn't a bad idea even for client workloads.
Keller joined AMD in August 2012, that's too late for him to have influenced the basic design of Excavator - if it comes out in 1Q15. He might have helped with some improvements/optimizations, but that's it. The design phase for complex CPUs currently seems to be in the range of 4-5 years, so a from-the-ground-up "Keller design" might come out in 2016/17 (Intel has given a 5-year project time for Haswell, it took Apple 5 years from the aquisition of P.A. Semi to release of the A7, and even something as primitive as the original P4 took 4 years from first RTL implementation to release). But if the result should be remotely as good as A7, it will be worth the wait.Keller has guided the development of Excavator and that processor will show us what he and the best of AMD's architects can do to get the most out of AMD's CMT CPUs. Because of this, EX will almost assuredly include more radical changes than the PD->SR uarch update.
SMT doesn't add a "20% thread"; when a core starts running in SMT, you simply get two threads running at roughly 60% of a single one, while on a BD family module you get two threads at ~90% performance of a single thread. Both approaches are transparent to the programmer and work without problems most of the time. Occasionally there are scaling problems when shared resources are insufficient to satisfy both threads, but this limitation is shared by both architectures. This is less common in a AMDs CMT architecture because fewer resources are shared, but it still happens. There have been cases when negative scaling was observed on Bulldozer when going from 4 to 8 threads (e.g. CLOMP v3.3 @ Phoronix). This should also become very visible with Kaveri when comparing integer to FP scaling.I've allways thought of SMT as the bastard child and here is why. Suppose you have one core. Now you SMT enable it. That means that you get to tap into that ~20% unused resources of the core if you just so happen to have another thread lying around that fits the bill.. and that bill really has to fit, dont it?
I like my hyperthreading, its a little something extra extra here and there, it is spice, but thats it.
From an coding angle and the operation system.... this must be a nightmare, I got these 4 real cores and then these 'maybe' 20% threads .. and if I put the wrong things (ie. fitting the bill) in these 20% threads the real cores/threads begins to suffer as well. We'll need some pretty smart AI to guide those schedulars soon.
That will depend on the workload. If you expect a high cache miss rate but want high utilization of the execution units, 8-way could be useful. I don't know the T5s details, but I'd guess that it has switchable SMT modes like Power does. Power7 can be statically set to 1/2/4 threads per core, so that you can configure your system for your specific workload, Intels SMT can be disabled as well. This is another advantage of SMT: you can adjust the amounts of thread per core for specific scenarios while paying only a small die area penalty. With CMT this is far less useful/the penalties are higher. Hm, although the costs for 4/8-way SMT will also be higher than 5%; it would be nice to know the specific costs of the Power7 and T5 implementations.In any case, even a 20% speed up for 5% more xtors is a good deal. Sparc T5s are now running 8 way SMT/core. I wonder how it's implemented and what the performance speed up is with that many threads. I know simulations done by DEC showed a drop of in efficiency/xtor after 4 way SMT/core (2nd ed. of Hennessy and Patterson, IIRC).
I don't think Excavator will really need 20nm. There's been lots of talk that the performance benefits of 20nm will be much less than in previous generations and that the cost/transistor won't go down much either, at least initially. And while the WSA is in force, AMD is operating under special restrictions. It may be much better to have a sub-optimal Excavator to produce at GFL than trying to compete with an older architecture. If Excavator really fixes most weak points of the BD family, AMD should get it into the market ASAP and then shrink to 20nm when feasible.Something like the Trinity->Richland scenario, that may well be the case, especially if Excavator *needs* 20 nm.
Fair enough.True, but AFAIK nobody has used CMT in a high-performance CPU. Seems to indicate that it isn't regarded as useful for producing competitive products.
One thing that has always irked me was that 5% die penalty statement, which I believe originated from the P4 era?Power7 can be statically set to 1/2/4 threads per core, so that you can configure your system for your specific workload, Intels SMT can be disabled as well. This is another advantage of SMT: you can adjust the amounts of thread per core for specific scenarios while paying only a small die area penalty. With CMT this is far less useful/the penalties are higher. Hm, although the costs for 4/8-way SMT will also be higher than 5%; it would be nice to know the specific costs of the Power7 and T5 implementations.
Keller joined AMD in August 2012, that's too late for him to have influenced the basic design of Excavator - if it comes out in 1Q15. He might have helped with some improvements/optimizations, but that's it. The design phase for complex CPUs currently seems to be in the range of 4-5 years, so a from-the-ground-up "Keller design" might come out in 2016/17 (Intel has given a 5-year project time for Haswell, it took Apple 5 years from the aquisition of P.A. Semi to release of the A7, and even something as primitive as the original P4 took 4 years from first RTL implementation to release). But if the result should be remotely as good as A7, it will be worth the wait.
I don't think Excavator will really need 20nm. There's been lots of talk that the performance benefits of 20nm will be much less than in previous generations and that the cost/transistor won't go down much either, at least initially. And while the WSA is in force, AMD is operating under special restrictions. It may be much better to have a sub-optimal Excavator to produce at GFL than trying to compete with an older architecture. If Excavator really fixes most weak points of the BD family, AMD should get it into the market ASAP and then shrink to 20nm when feasible.
I was expecting EX on 20nm, so not till 1H2016, in that case, I think Keller would have had allot of input into EX. His main influence, of course, is the re-org he did of the CPU teams in 2012 - mainly by picking the 'winners' who would stay and lead the various teams and groups. Given the lower head count, I think AMD is relying more on automation tools and doing less hand placement out of necessity - this will shorten development times, but at a cost. I wonder if Kaveri 'B' came about because AMD realized GF wasn't going to be able to hit their clock targets and Kaveri needed some more hand tuning to get better clocks/higher throughput.
If EX is going to be 28nm, and is thus further along than I thought, then I agree - AMD needs to get it to market as fast as possible. I really hope that EX has at least the option of using triple or quad channel memory, even if most vendors don't use it. It would allow AMD to offer an 'performance' APU to their fans that wouldn't be crippled by bandwidth. Assuming AMD has enough fans left to attract Asus and Gigabyte to supply the requisite motherboards.
Lastly - from the rummage room of my mind - I think that if AMD wants a place at the table for even the low-end x86 server market, that they will have to add SMT since they just can't scale CMT well enough to improve perf/watt for high utilization multithreaded apps. But that is going to take allot of effort and will be a ways out.
On the other hand, 20nm could be an inflection point for AMD since it will be more than a full node drop from 32nm and could allow them to place something like 16 EX cores on a die and see very significant gains in performance and perf/watt that may allow them to re-enter the market. GFL will have to come through with a process that's the right fit for such a product to exist. They wouldn't be a big player, but they don't have to be if significantly higher margins than they get for desktop are available to them.
In any case, thanks for the engaging comments
2016?! I know GlobalFoundries are bad, but surely 20nm isn't running *that* late.
2016?! I know GlobalFoundries are bad, but surely 20nm isn't running *that* late.
Who knows, 28nm HP parts products is next year for example.
Branch Prediction -> Logic|Doubled / RAM|6 to 8It's got double the ALUs/AGUs and FPU width, and the data caches expand to 32KB each. It'll certainly be faster per clock. If they end up fixing their memory controller issues, it could be a very compelling design.