The stacked chips are bonded together, so they are like one thick chip, so heat goes through that chip just like it does any other chip. To get the power map of a stacked chip, you just sum up the power maps of all the individual layers-the thickness of each layer is so small that even when they're stacked on top of each other it's like they're one layer from a conventional chip. Bryan said in his talk that thermals are absolutely not a concern for 3D stacking.
It is not stacked DDRx. DDRx refers to the data rate of the *IO pins,* so what goes on inside the DRAM chip doesn't matter as long as it can keep up with the IO rate. HBM will have a layout and organization that will allow it to achieve 1TB/s of throughput (as per the slide above 1024 IOs x 1GHz each), compared to the 1-2 GB/s that a DDR3 chip provides.
HBM is a 2.5D technology, where there is a stack of memory *next to* the chip, connected by a silicon interposer. But in general, the various layers of a 3D stack do not need to be the same size. Smaller layers can go on top of larger layers.
I would almost guarantee a "no." APUs don't have the margins to absorb that cost.Will APUs get this technology before discrete cards? If so, it could cause quite an upheaval in the GPU market.
I would almost guarantee a "no." APUs don't have the margins to absorb that cost.Will APUs get this technology before discrete cards? If so, it could cause quite an upheaval in the GPU market.
(Bad) Automobile analogy incoming:In theory yes. In reality unlikely . It would make Carizzo's iGPU probably the fastest on the market and would erase all the lower end discrete GPUs from competition. Add a year or two on anything they claim and you will get approx. time frame for products.
And exactly how much would they be putting on there? There's no way they'd be able to do 4 or 8GB for $20. 2GB, maybe. But $2-3? We're talking about tiny amounts of RAM... I'd imagine performance would be rather limited in such a configuration.Bryan Black started his talk by saying that Intel (where he used to work) shot down 3D stacking 10 years ago because it could add "10-15 cents per chip," but that AMD was excited enough about it that they would do it even if it added "200 dollars" per chip. He said it looks like when it finally arrives that it will add 2 or 3 dollars per chip.
Now, if this 2-3 dollars is including the price of the HBM, or just an additional integration cost on top of the price of the DRAM dice, I'm not sure. But my guess is that integrating HBM with an APU would cost AMD anywhere from $2 to a maximum of $20 per chip, which is totally reasonable for an APU.
And exactly how much would they be putting on there? There's no way they'd be able to do 4 or 8GB for $20. 2GB, maybe. But $2-3? We're talking about tiny amounts of RAM... I'd imagine performance would be rather limited in such a configuration.
How soon until the Rambus lawsuit?
That 2-3 dollars is propably diffrent / better / bigger memory controler and connectors between chip and stacked memory on board and all other changes that will allow CPU/APU to use such high bandwidth and take advantage of it.Bryan Black started his talk by saying that Intel (where he used to work) shot down 3D stacking 10 years ago because it could add "10-15 cents per chip," but that AMD was excited enough about it that they would do it even if it added "200 dollars" per chip. He said it looks like when it finally arrives that it will add 2 or 3 dollars per chip.
Now, if this 2-3 dollars is including the price of the HBM, or just an additional integration cost on top of the price of the DRAM dice, I'm not sure. But my guess is that integrating HBM with an APU would cost AMD anywhere from $2 to a maximum of $20 per chip, which is totally reasonable for an APU.
Xeon Phi with stacked memory
I bet the likes of Samsung & Co have a thing or two to say about that claim ~
Coalition of 20+ Tech Firms Backs MRAM as Potential DRAM, NAND Replacement
where was it announced ?
I can't find it mentioned here
http://newsroom.intel.com/community...-next-generation-intelr-xeon-phi-tm-processor
the memory modules in slide 7 of the PDF look very thin
do you have a link to new information ?
200W TDP. I don't see how to escape water cooling for that.
Keep in mind, graphics cards have even higher TDPs. Since this is a PCI-E card, there's no issue with air cooling here.200W TDP. I don't see how to escape water cooling for that.
Yeah, it'll be a quite disruptive technology. The sooner, the better.That's a good point. Right now, a 4Gb chip of DDR3 is about $4, so getting 4GB worth of DDR3 chips would cost at least $32. This doesn't translate directly to costs in 3D packaged memories, though, and as soon as 3D memories are common I'm sure we'll be at least one DRAM node into the future by then, so prices will be lower. I wouldn't be surprised if APUs with 8GB of HBM cost $20-$30 more than their non-HBM counterparts when they debut. Eh, maybe $50 more, but 8GB is enough capacity to be the entire main memory, so you're saving cost elsewhere in the system.
One thing is for sure, though, that having 1TB/s of DRAM bandwidth will be excellent for the future of APUs.
200W TDP. I don't see how to escape water cooling for that.
MCDRAM=Memory Cube DRAM.
Keep in mind, graphics cards have even higher TDPs. Since this is a PCI-E card, there's no issue with air cooling here.
Knight's Landing is available in a standard CPU socket, as well as on a PCIe card.
Oh really? That's interesting.