AMD announces two new FX processors

[Troll Trolling]

so it now matches the 2400 but w/ more power consumption

From what I could gather, the 6 and 4 cores (mainly the 6 cores) are not even close to being as bad in perf/watt than their 8 cores counterpart.

http://ht4u.net/reviews/2011/amd_fx_6100_4100_review/index7.php

And since they undervolt really well, I guess they've set the voltage really conservative on the first FXs, that means there is a lot of headroom, so I wouldn't doubt that it uses about the same power as the reviewed units.

 

[BD231]

I thought bulldozer should be $231. At least that is what I think when I see you post.

Being that you own an AMD FX processor thinking is probably not something you practice often.

I would suggest you do some thinking of your own. If you had been doing so in the past, you wouldn't have made this post
-ViRGE

 

[blckgrffn]

Being that you own an AMD FX processor thinking is probably not something you practice often.

Way to keep it classy :thumbsup:

Both of you.

 

[Chiropteran]

You are the one who picked the name, don't get angry at me, B[ull]D[ozer]231

 

[Topweasel]

These are finally rolling out, eh?

Well, you get four threads at 4.2 ghz for your 125W versus 8 @ 3.6 with the 8150, in less threaded games/usage you could argue that the clockspeed is more useful.

But really, not that interesting. Had they been 95W parts (and I think there are a couple new ones with more modest clock bumps coming as well) they would have garnered a bit more interest. What I think is surprising is that we have gone this long with such a limited number of SKU's. They must have horrible yields, horrible sales, or both IMHO.

I think the plan was by this point they would have stopped re-binning 4 module parts. So I am guessing is that either.

A.) Yields are not good and they are having tons off issues with bad modules. B.) That the new CEO killed the alternate die's, rather then spend more in making BD cheaper to sell, rather just keep spending more in silicon. Or C.) Along the same lines the 4k and 6k are not selling enough to warrant their own dies.

While nearly a copy yours had to do with a limited amount of SKU's. I think the lack of SKU's are a symptom of a single die. Because right now there are 8 sku's off of a single die. I think if they got the cheaper dies out, we would be flooded with SKUs, with a new CPU for every $10 from $80-$200.

 

[BD231]

Watching someone I've berated so thoroughly strike out on a personal vendetta is in fact, entirely amusing .

 

[blckgrffn]

I think the plan was by this point they would have stopped re-binning 4 module parts. So I am guessing is that either.

A.) Yields are not good and they are having tons off issues with bad modules. B.) That the new CEO killed the alternate die's, rather then spend more in making BD cheaper to sell, rather just keep spending more in silicon. Or C.) Along the same lines the 4k and 6k are not selling enough to warrant their own dies.

While nearly a copy yours had to do with a limited amount of SKU's. I think the lack of SKU's are a symptom of a single die. Because right now there are 8 sku's off of a single die. I think if they got the cheaper dies out, we would be flooded with SKUs, with a new CPU for every $10 from $80-$200.

You may very well be right. The fact they did not make a dedicated 2 or 3 module part with less/no L3 cache (seriously, are there test out there for how much difference this would make? It's latency is so atrocious, if you don't have a lot of cores to keep memory consistency a super high priority, we'd all be better off with a larger/faster L2 and lopping off the L3 altogether I'd think) says a lot about how AMD feels about BD.

I suppose they are banking on Trinity for that niche. CPU world lists quite a few SKU's for that guy already...

If anyone has a BD that they would disable the L3 on and compare performance in gaming, etc. that would be interesting. My Google-fu is failing me.

The member formerly known as SLK? Are you reading this thread?

Don't make me drive to MC and buy a BD to find out. Please.

 

[pelov]

What I don't understand is why they're aiming for higher core clocks when they could go for a reduction in cache latency. If anything, they should aim for lower latency in the L2 and L3 cache and if possible raise the L3 cache's clock speed while reducing the core clock speed. What good is raising the core clock speed going to do when the cache sucks?

Bingo. That's what worried me about Bulldozer and it seems they're going ahead full steam with the same ideas which previously caused BD to perform the way it did. High clocks usually mean slower cache, and that slow cache was the likely culprit for the poor IPC. I think whatever they decided for Trinity may have been done so prior to the release of Bulldozer, because even higher clocks is a sign of AMD going backwards by being stubborn.

If Trinity can match Llano (10-15%? a big if considering those clock speeds) then any higher clocks will be a bonus and very welcome. Unfortunately, unless they've got a wizard or IDC back there, I'd imagine they're still short of their initial BD IPC goal, even in Piledriver.

It'll come down to price. If GLoFo has good yields and AMD hasn't spent so much die space on so much worthless cache then Vishera and Trinity may be good bargain chips and AMD can regain that price-to-performance crown under the $200 mark

 

[blckgrffn]

Bingo. That's what worried me about Bulldozer and it seems they're going ahead full steam with the same ideas which previously caused BD to perform the way it did. High clocks usually mean slower cache, and that slow cache was the likely culprit for the poor IPC. I think whatever they decided for Trinity may have been done so prior to the release of Bulldozer, because even higher clocks is a sign of AMD going backwards by being stubborn.

If Trinity can match Llano (10-15%? a big if considering those clock speeds) then any higher clocks will be a bonus and very welcome. Unfortunately, unless they've got a wizard or IDC back there, I'd imagine they're still short of their initial BD IPC goal, even in Piledriver.

Trinity has no asynchronous cache as far as I can tell, and the L1 data cache is back up to a sane 32 bytes up from the P4-esque level 16 byte data cache (which made a least a little sense, as it was inclusive) there currently. So, a PD module will have as much L1 data and instruction as a Thuban core, yet these caches are still slower as I have not seen them reducing how n-associated any of the caches are.

Get the same amount of work done with smaller and slower cache per clock cycle? How can that make any freaking sense at all? You'd have be to be really excellent at branch prediction, etc.

Plenty of articles out there comment on the BD L1 data cache reducing performance as it is constantly being emptied/filled because it is too small.

Perhaps its a miracle that BD doesn't suck worse that it does currently. Those poor CPU engineers... toiling away on decisions that seem to have come from left field.

http://www.lostcircuits.com/mambo//...sk=view&id=102&Itemid=42&limit=1&limitstart=2 <-- Interesting discussion of BD Cache IMHO.

 

[guskline]

Glad to see AMD is making some changes. I'll wait for the PileDriver.

 

[pelov]

Get the same amount of work done with smaller and slower cache per clock cycle? How can that make any freaking sense at all? You'd have be to be really excellent at branch prediction, etc.

Plenty of articles out there comment on the BD L1 data cache reducing performance as it is constantly being emptied/filled because it is too small.

Perhaps its a miracle that BD doesn't suck worse that it does currently. Those poor CPU engineers... toiling away on decisions that seem to have come from left field.

Addressing L1 data is only half of what needs to be done on the L1 side, as the L1 writes rely heavily on the small WCC midpoint which in turn relies on the unbelievably slow and too hefty L2. The L1 data will likely improve performance a bit, but due to the way writes are done within the L1>WCC>L2, they'll have a lot more to do.

It stinks of netburst. It smells like netburst. AMD can't afford a netburst and poorly though-out designs driven by egomaniacs. What they do right on the GPU side with Fusion and HSA they've countered with poor choices on the CPU side.

There was a few things on my checklist for Trinity and Piledriver that had to be marked before I thought Vishera stood a chance in hell. The first of those was a stabilization or even a slight decrease in clock speed. Though the resonance mesh tech is an asterisk in this equation, it still won't account for any change in IPC. I'm sure Trinity will be a great buy despite still lackluster IPC, but that's mainly due to perf-per-watt, price and GPU performance. Vishera, on the other hand, is going to sink.

 

[blckgrffn]

Addressing L1 data is only half of what needs to be done on the L1 side, as the L1 writes rely heavily on the small WCC midpoint which in turn relies on the unbelievably slow and too hefty L2. The L1 data will likely improve performance a bit, but due to the way writes are done within the L1>WCC>L2, they'll have a lot more to do.

It stinks of netburst. It smells like netburst. AMD can't afford a netburst and poorly though-out designs driven by egomaniacs. What they do right on the GPU side with Fusion and HSA they've countered with poor choices on the CPU side.

There was a few things on my checklist for Trinity and Piledriver that had to be marked before I thought Vishera stood a chance in hell. The first of those was a stabilization or even a slight decrease in clock speed. Though the resonance mesh tech is an asterisk in this equation, it still won't account for any change in IPC. I'm sure Trinity will be a great buy despite still lackluster IPC, but that's mainly due to perf-per-watt, price and GPU performance. Vishera, on the other hand, is going to sink.

Could you expand on that a bit (the wcc midpoint) as I don't know enough to follow you... I tried googling "wcc midpoint bulldozer" and that points back to this thread. Even a link to some other resource (so you don't have to spend time/effort typing) would be much appreciated.

http://www.ilsistemista.net/index.p...n-whats-wrong-with-amd-bulldozer.html?start=4 <-- this is what you are referring to? Reading now...
Sidepoint, holy crap Google indexes fast.

WTF using write through L1 data cache? Has this been confirmed for PD? I had read that before (about BD), and I know the difference (write-back vs write-through), the actual implications had been lost to me.

That, and for others in the thread, the "WCC" is the Write Coalesce Cache, a 4KB mid (?) cache that attempts to mask the high write latency of the L1 data cache by committing many L1 to L2 write commits into one operation.

I assume that once data is in that 4KB cache it is considered to have been written through? If they don't make that larger then it will likely be even less useful than it is now.

Rip off that darn L3 cache and please put the transistor budget into the L2 cache AMD. I know smarter people than me are making these decisions, but as it is laid out now it seems nearly nonsensical. All in the name of clockspeed? Netburst, we meet again.

Or, as you said, shrink and improve L2 and leave the L3. Something.

 

[pelov]

Yep, that's the one.

It's an issue they should have seen from a mile away, but because it was meant as a server chip first, it was something they were willing to sacrifice on the desktop, where gobs of cache make less sense.

They're stuck in a rut, the way I see it. Unless software makes exponential strides in multi-threading (the biggest would be a truly seamless and efficient way of threading that I've only read in a Scientific American article last year. I can't find the link but if I do I'll post it here), then they won't be getting anywhere fast.

CMT is ... weird. There's 2 ways of looking at it:
1 - A core that's beefed up to a point where it can resemble 2 cores (integer in this case), or
2 - 2 cores that were stripped down such that they share resources and offer performance close to what would be achieved if they had been separate.

One of those tends to look better than the other. But I think regardless of the way you look at it, unless they're able to significantly increase IPC within the modules then AMD will simply start clocking themselves out of contention on both the server and the desktop. It's all about IPC here, and the best way to do that (from what I've been reading) would be with restructuring of the caches, and mainly the L1 and L2. But because of the way it's designed, they're intertwined. Thus addressing the size of the L1 data does little as far as smoothing those issues out, and astronomical clock speeds only point to the problem remaining. 4KB WCC doesn't look like its enough, but because of the small L1 speeds and write-through, it's all about the L2. And, for BD, it's likely the weakest point in the chip... I can't recall how many stages the pipeline had, but quite clearly the L2 is nowhere near fast enough to be so heavily relied on as far as L1 goes. The L2 has to be slow in order to have high clock speeds, which was the initial goal of BD in the first place 4.5ghz, but where will the IPC gains come from if the clock speeds are so high in Trinity? I don't see them addressing the speeds of the L2 much if they even decide to address them at all. Unless they have a secret weapon for getting that L2 up to par any clock speed bumps are trying to overcome the still poor IPC

err, just to add

The BD pipeline is ~%25 longer than the Deneb pipeline. I'm not sure how much an impact the CMT approach had to do with lengthening the pipeline, but in its current form, BD doesn't clock high enough to make up that gap and nowhere close to 25%. With a longer pipeline they're almost forced to clock higher because that's the easiest way to do things You can point to Power7 and say that it can work, and yes it can, but I don't see any Power7 desktops.

 

[blckgrffn]

I think that they are *close* to having something really great.

IF they can improve L1 Write Latency (hello Write-Back cache, we've missed you), eliminate the WCC altogether while improving the L2 Latency considerably while getting process improvements...

Honestly, I am cool with 5Ghz if it only consumes 95W Performance/Watt is the defining attribute IMHO, whatever the IPC.

Well then we'd at least get the BD and SB competitor we were waiting for. Having AMD compete against the previous generation of Intel CPUs on actual performance is probably the realistic goal at this point, given that they have shifted their focus. /apologizing-for-amd

I am going to hope they pull a Phenom II out of FX2. That is a brighter future to consider, IMHO, than the one where they just give up.

 

[pelov]

I'm on the side of IPC gains here, not that drastic increases in CPU frequency won't amount to the same performance gain assuming they're able to get there. But with the cache speeds being purposely slow as a result of the lengthened pipeline, I'm not seeing any significant gains in L2 speeds. I think for them to address the biggest issue with BD's performance, the L2, they would need to decrease the length of that pipeline and even stall or decrease the clock speeds. Currently, all signs point to 5ghz+ and that's not something I wanted to see :/

I guess there is some light at the end of the tunnel, though. They believed they could have achieved an IPC equal to the Thubans despite having that longer pipeline, thus any clock speed increases (planned for mid 4ghz) would have put them in the black according to how high it was able to clock. That would have put them within SB range of performance. Realistically, they need to hit 4ghz+ on Vishera with IPC that matches Thuban. I guess we'll see how hopeful that is once Trinity is released and we compare it to Llano. You definitely seem more hopeful than I am =P

http://www.anandtech.com/show/5600/...-u8540-35-lower-power-much-higher-frequencies

Not sure that will ever make it to production, but it's nice to see that the chase for moar gigrhurtz isn't in vain

 

[lifeblood]

Which is more likely, AMD getting better IPC in Piledriver or high Gigahertz from TMSC? I would think it would require a major CPU redesign to improve IPC which is not likely. A more optimized design plus more raw Gigahertz from TMSC seems much more likely.

How hard is it to improve the cache in 9 months (assuming they stick to the Q3 release)? I'm sure it would help, but is it realistic?

 

[formulav8]

Will officially bypass the P4 3.8ghz as the highest clocked oem chip.

 

[formulav8]

Which is more likely, AMD getting better IPC in Piledriver or high Gigahertz from TMSC? I would think it would require a major CPU redesign to improve IPC which is not likely. A more optimized design plus more raw Gigahertz from TMSC seems much more likely.

How hard is it to improve the cache in 9 months (assuming they stick to the Q3 release)? I'm sure it would help, but is it realistic?

Well PD they have had to be working on for quite a while to be able to release revised core level updates this year. FX cpu's are made at Global Foundries.

Also, PD is supposed to be up to 15% higher ipc performance. I'm sure a bit of it is AMD focusing on the caches and buffers. The L2 and L3 caches majorly need latency lowered and the clockspeed of the L3 cache could use a increase as well. A bigger L1 cache would help a bit as well.

After a couple core revisions BD will be quite nice. Even now BD is not bad. It should be priced better but it does everything consumers needs a computer to do and more.

 

[Phynaz]

Will officially bypass the P4 3.8ghz as the highest clocked oem chip.

Unless you want to count the rate the ALU's actually ran at

But yes, the clock generator rate on these will officially be the highest ever for an x86 CPU.

 

[blckgrffn]

Unless you want to count the rate the ALU's actually ran at

But yes, the clock generator rate on these will officially be the highest ever for an x86 CPU.

What a distinction :awe:

At least it thoroughly pounds that old P4 in perf/watt. Take that Intel!

 

[Rvenger]

they increased both, L3 and clocks

If that's the case then the 8170 will look promising after all. I hope this ends up like the ph II launch

 

[Rvenger]

If anyone has a BD that they would disable the L3 on and compare performance in gaming, etc. that would be interesting. My Google-fu is failing me.

The member formerly known as SLK? Are you reading this thread?

Don't make me drive to MC and buy a BD to find out. Please.

I wonder if my bios would allow me to disable the L3 Cache. I will take a look into it when I get home. How do you want me to test this? What benches?

 

[blckgrffn]

I wonder if my bios would allow me to disable the L3 Cache. I will take a look into it when I get home. How do you want me to test this? What benches?

Anything you already have data on would be fine. Just to get an idea of the % performance increase that L3 brings to the table

Awesome

 

[Rvenger]

I'll run super PI, cinebench, some fritz chess, 3dmark vantage, heck some 7zip too since thats the new popular selection.

 

[pelov]

Which is more likely, AMD getting better IPC in Piledriver or high Gigahertz from TMSC? I would think it would require a major CPU redesign to improve IPC which is not likely. A more optimized design plus more raw Gigahertz from TMSC seems much more likely.

How hard is it to improve the cache in 9 months (assuming they stick to the Q3 release)? I'm sure it would help, but is it realistic?

Remember that TSMC doesn't do SOI and that's a big part of AMD's plans. I believe they're sticking to SOI on 28nm as well, so that would make the APUs (28nm APUs) a GloFo thing as well. It wouldn't work on TSMC, never mind the transitioning time that it would take. But don't be so quick to blame this on GloFo. I've been saying this for months now, but the power consumption and clocks were more related to the architecture and design rather than poor yields. As I've said before, even Intel couldn't produce the chips AMD initially wanted for Bulldozer, and any problems GloFo had were on Llano (GloFo had to hit the ground running when it came to making the GPUs on Llano, but they're very good at making CPUs).

AMD claimed a 10-15% performance increase from perf-per-watt, IPC and clock speeds per year. I highly doubt we'll get 15% IPC from that. That's the bad news. The good news is that they increased their performance estimates on Trinity to represent "uplift" rather than "under digital media workloads." So here's to hoping it isn't about instruction sets and they pull another Bulldozer (Congratulations on your new processor! I sure hope you like AVX!)

I'll run super PI, cinebench, some fritz chess, 3dmark vantage, heck some 7zip too since thats the new popular selection.

Can you do me a favor and run some of those at Llano clock speeds? I'm wondering how far off the IPC is and just how much ground AMD will have to make up for Trinity.