AMD Bristol/Stoney Ridge Thread

[amd6502]

Well, if BR/Stoney are unable to dual-purpose as GPU die then maybe this is better for a native dual core Zen APU (since the new fabric could might make this easier?). Vega is a little bit more up to date too.

 

[ET]

Interestingly Atari is now saying that the VCS will only be released in 2019. Perhaps it will end up using Raven Ridge.

 

[dark zero]

Indeed, seems that they moved to Raven Ridge. I guess AMD suggested that. Poor Nosta...

 

[NostaSeronx]

To microcode:600611A from microcode:6006118 for FX-9800P.
To 2018/05/02 Version: 1.31 from 2017/08/22 Version: 1.19
-> change code base. (Come on Acer! Yeesh, that could mean literally ANYTHING! At least, no more beta H20FFT for firmware flashing yay!)

---
22FDX+ is near finished. GFX10.1 and the new core is expected for the 22FDX+ design. Low cost HBM (2 GB HBM2 GenY and 4 GB HBM3 GenX) Draft is also getting developed on 22FDX(and 18FDS).

Celluar SoC AMD India is where most of the FDSOI treasure trove is at.

 

[amd6502]

???

 

[NostaSeronx]

???

1. 22FDX+ will follow an aggressive tapeout schedule.
2. Zen only goes from passive-cooled notebooks to supercomputers. The new Cluster-based Multithreading core will be internet of things to tablets. (Set-top boxes, and enterprise mobile are the huge markets being targeted though.) ((There is hints of semi-custom... so far but it is being designed by Medfield and Moorefield (maybe Riverton(the ones that didn't go to Spreadtrum)) doods)) (((Currently, investigating if Qualcomm would allow AMD to invade their market space, if it is rebranded(x86 Kyro 1000 and Navi Adreno 1000, etc).)))
3. The 22FDX+/12FDX(+) and 18FDS nodes will have access to the low cost 512-bit HBM2/3-based DRAMs before 7/5-nm ever get it.
---
If you are talking about the microcode and firmware version stuff. Then, if one owns Bristol or Stoney one should look and upgrade said stuff.

 

[NTMBK]

1. 22FDX+ will follow an aggressive tapeout schedule.
2. Zen only goes from passive-cooled notebooks to supercomputers. The new Cluster-based Multithreading core will be internet of things to tablets. (Set-top boxes, and enterprise mobile are the huge markets being targeted though.) ((There is hints of semi-custom... so far but it is being designed by Medfield and Moorefield (maybe Riverton(the ones that didn't go to Spreadtrum)) doods)) (((Currently, investigating if Qualcomm would allow AMD to invade their market space, if it is rebranded(x86 Kyro 1000 and Navi Adreno 1000, etc).)))
3. The 22FDX+/12FDX(+) and 18FDS nodes will have access to the low cost 512-bit HBM2/3-based DRAMs before 7/5-nm ever get it.
---
If you are talking about the microcode and firmware version stuff. Then, if one owns Bristol or Stoney one should look and upgrade said stuff.

If any embedded or semi-custom projects need a slow CPU on a sub-28nm process, AMD already has 14nm ports of Jaguar. Just slap down a couple of quad core clusters, run them at >2GHz, job done.

 

[NostaSeronx]

If any embedded or semi-custom projects need a slow CPU on a sub-28nm process, AMD already has 14nm ports of Jaguar. Just slap down a couple of quad core clusters, run them at >2GHz, job done.

The 16/14-nm ports of Jaguar was a specific demand by Sony and Microsoft. GlobalFoundries has given an ultimatum to all of its top tier customers do both or do none. There is also specific requirements that FDSOI does that FinFET can never do well, Analog-Mixed Signal - Radio Frequency - Optielectronics, etc(1). (1) SoC for set-top boxes, embedded computer vision, microcontrollers, mixed-signal applications such as transceivers, GPS/satellite receivers, wi-fi/BT combos and mmWave radar systems.

Jaguar on the consumer side has been dethroned with Excavator(Stoney Ridge). So, the only requirement AMD has to do is make something more efficient than Excavator and do it on FDSOI. With CMT AMD has the advantage of going EPI over IPC with the FDSOI lineup. This in turn makes it non-competitive with FinFET skus, etc. While allowing both SKUs to utilize the same parts; CCX, Branch Predictor, ISA generation. The FDSOI however does IVR better, diverse application better, and more better than FinFETs and has three Foundries by 2019 and possibly more in 2020.

The more fringe cases is that both can be applied.
FinFET as primary and FDSOI as secondary; FinFET CPU/GPU(AM4 and PCIe) and FDSOI APU(BGA) as Southern APU(Southbridge), etc. (Buy a motherboard and it works, then add the AM4 cpu and GPU in Pcie, etc.)

 

[NTMBK]

The 16/14-nm ports of Jaguar was a specific demand by Sony and Microsoft.[/url]

Given that AMD own the Jaguar IP outright, I don't think that Microsoft or Sony could do anything to stop them using it in future projects.

GlobalFoundries has given an ultimatum to all of its top tier customers do both or do none.

Well that would be a fantastic way to get customers to tell them to shove it, and go to TSMC instead. Good job that there's zero evidence of it happening.

There is also specific requirements that FDSOI does that FinFET can never do well, Analog-Mixed Signal - Radio Frequency - Optielectronics, etc(1). (1) SoC for set-top boxes, embedded computer vision, microcontrollers, mixed-signal applications such as transceivers, GPS/satellite receivers, wi-fi/BT combos and mmWave radar systems.

AMD don't have a radio division, so they can't go adding any of that stuff.

Jaguar on the consumer side has been dethroned with Excavator(Stoney Ridge). So, the only requirement AMD has to do is make something more efficient than Excavator and do it on FDSOI. With CMT AMD has the advantage of going EPI over IPC with the FDSOI lineup. This in turn makes it non-competitive with FinFET skus, etc. While allowing both SKUs to utilize the same parts; CCX, Branch Predictor, ISA generation. The FDSOI however does IVR better, diverse application better, and more better than FinFETs and has three Foundries by 2019 and possibly more in 2020.

You're coming at this backwards. You're saying that they "need" to make a successor to Excavator. But why? That theoretical CPU would need to fit into the gap between a 14nm Jaguar, and Zen. A high clocked Jaguar cluster can cover a tonne of embedded cases where CPU performance doesn't really matter, and for anything above that you have a Zen cluster. Yes, that leaves a gap in between where Jaguar isn't quite fast enough, but Zen is overkill... but how big is that gap? Can AMD make their money back on creating a whole new CPU for that market, as opposed to just selling a low clocked Zen chip that didn't make the higher speed bins?

The purpose of the embedded business unit was to reuse the chips and IP that AMD was already creating, and generate more revenue for minimal expenditure. There's a handful of big ticket semicustom customers, and even they have been using the existing IP with minimal changes... and this is for customers who are buying tens of millions of units. Every other product has been a minor rebadge or respin of a chip that was built for the consumer market, with added software and long term support. Unless a customer the size of Microsoft or Sony was explicitly requesting (and paying for) a CPU with worse performance than Zen, why would AMD go make it?

The more fringe cases is that both can be applied.
FinFET as primary and FDSOI as secondary; FinFET CPU/GPU(AM4 and PCIe) and FDSOI APU(BGA) as Southern APU(Southbridge), etc. (Buy a motherboard and it works, then add the AM4 cpu and GPU in Pcie, etc.)

Congratulations, you've just made a system which is either way overpriced for a low end embedded system (APUbridge only), or has an overpriced motherboard (big APU).

 

[NostaSeronx]

Well that would be a fantastic way to get customers to tell them to shove it, and go to TSMC instead. Good job that there's zero evidence of it happening.

Samsung is doing it as well, go FDSOI or go away.

AMD don't have a radio division, so they can't go adding any of that stuff.

AMD doesn't need a home grown radio division when they have RF IP access from GlobalFoundries. GlobalFoundries even recommends the top tier to share RF IP or get out. So Qualcomm absolutely has to provide AMD with Snapdragon Xxx LTE modems because of GlobalFoundries.

"'Qualcomm Technologies believes the Always Connected PC is the future of personal computing, and we are working with AMD to bring each company's expertise to bear for these exciting products," said Alex Katouzian, senior vice president and general manager, mobile, Qualcomm Technologies, Inc. "Combining AMD processors with our cutting-edge LTE connectivity technology results in Always Connected Client Notebooks for consumers in a mobile-first future."'

You're coming at this backwards. You're saying that they "need" to make a successor to Excavator. But why? That theoretical CPU would need to fit into the gap between a 14nm Jaguar, and Zen. A high clocked Jaguar cluster can cover a tonne of embedded cases where CPU performance doesn't really matter, and for anything above that you have a Zen cluster.

There is specific benefits that FDSOI and cluster-based multithreading processors have over FinFETs and core multiprocessing processors. CMT guarantees higher energy per cycle and SMT guarantees higher instructions per cycle. While both utilizing the same intellectual property and physical macros. What goes in one goes in the other as AMD's CMT is SMT. The particularly need is to creating something in between Excavator and Jaguar with a huge slant towards EPI/EPC.

1. What is used in Zen will be transferred into the new core. (Zen -> Zen5 decisions would effect gen 1 -> gen 5 of the new ULP/ULV core)
2. Jaguar isn't high performance enough. Can't simply get higher frequency from a port.
3. Excavator isn't low power enough. Can't simply get lower energy from a port.
4. 22FDX intrinsically has better power statistics than 14LPP/12LP for ULV.
5. The new core only is required to achieve a minor IPC/WPC boost over XV/JG while having a massive EPI/EPC drop.
6. ISAs between the high work per cycle core(Zen) and the low energy per cycle core(XLP core 3: Bobcat -> Jaguar -> this) are required to be exactly the same. Optimization for one is optimization for the other, etc. CMT can benefit SMT, and SMT can benefit CMT.

Congratulations, you've just made a system which is either way overpriced for a low end embedded system (APUbridge only), or has an overpriced motherboard (big APU).

The 22FDX APU is cheaper than a 55-nm Promontory chip in the long run. With increased functionality over 55-nm; 22FDX can go faster in less area and provides longer longevity of the board at lower risk. Optielectronics is also definitely defined in 22FDX, so the change would have to happen regardless.

 

[NTMBK]

Samsung is doing it as well, go FDSOI or go away.AMD doesn't need a home grown radio division when they have RF IP access from GlobalFoundries. GlobalFoundries even recommends the top tier to share RF IP or get out. So Qualcomm absolutely has to provide AMD with Snapdragon Xxx LTE modems because of GlobalFoundries.

"'Qualcomm Technologies believes the Always Connected PC is the future of personal computing, and we are working with AMD to bring each company's expertise to bear for these exciting products," said Alex Katouzian, senior vice president and general manager, mobile, Qualcomm Technologies, Inc. "Combining AMD processors with our cutting-edge LTE connectivity technology results in Always Connected Client Notebooks for consumers in a mobile-first future."'

GloFo have been fighting tooth and nail to win custom away from TSMC. Samsung is trying desperately to win custom away from TSMC. They aren't going to force customers into their competitor's arms.

There is specific benefits that FDSOI and cluster-based multithreading processors have over FinFETs and core multiprocessing processors... *snip*

It's still a shitload of work to create *and validate* a core. Expensive work, using a limited resource (skilled CPU designers) that could be more valuable elsewhere. You've missed my point again- it's a theoretical core for a narrow niche.

The 22FDX APU is cheaper than a 55-nm Promontory chip in the long run. With increased functionality over 55-nm; 22FDX can go faster in less area and provides longer longevity of the board at lower risk. Optielectronics is also definitely defined in 22FDX, so the change would have to happen regardless.

Southbridge chips generally can't go any smaller because they need physical space to fit on all of the I/O pins. That's the whole reason they're made on such an old process- because you still need the same die area, even on a smaller process, so what's the point of shrinking? You've just replaced a cheap old chip with a more expensive modern chip of the same size.

 

[amd6502]

The 16/14-nm ports of Jaguar was a specific demand by Sony and Microsoft. GlobalFoundries has given an ultimatum to all of its top tier customers do both or do none. There is also specific requirements that FDSOI does that FinFET can never do well, Analog-Mixed Signal - Radio Frequency - Optielectronics, etc(1). (1) SoC for set-top boxes, embedded computer vision, microcontrollers, mixed-signal applications such as transceivers, GPS/satellite receivers, wi-fi/BT combos and mmWave radar systems.

Jaguar on the consumer side has been dethroned with Excavator(Stoney Ridge). So, the only requirement AMD has to do is make something more efficient than Excavator and do it on FDSOI. With CMT AMD has the advantage of going EPI over IPC with the FDSOI lineup. This in turn makes it non-competitive with FinFET skus, etc.

Well, as an XV fan it would be nice to believe, but I think Zen is highly efficient. At least when the core is loaded with two threads, it should beat XV (and Puma) quite a bit at EPI. (With only 1 thread a core I think they can still make efficiency good with gating. Somebody needs to do some wattage benchmarks with a 2200g or with another zen cpu with SMT turned off.) Maybe the potential for FDX tricks you mentioned before (with voltage biasing) is so great that this could be overcome, so that XV+ could beat Zen in EPI?

Like NTMBK says, the IO connections are the limit of how small you can make the die. For low powered small dies, SR is probably king for cheapest production cost small die. I don't think we've seen an AMD die in a while that's been well under 100mm2 (neither CPU nor GPU). So a good guess for that limit is ~100mm2.

22nm wouldn't seem much smaller. It could be the same die area and let you fit in a few more features. But how much more expensive is 22FDX over 28nm? If not much, I would think it'd be well worth it for the efficiency gains. Then the main question remains: can they justify the cost of the project for the sum of the expected future earnings from such a project?

There are other factors: do they have spare staff or do they want to focus everything on radeon and zen? will the project compete with old stock inventory or is this not an issue?

 

[Abwx]

Somebody needs to do some wattage benchmarks with a 2200g or with another zen cpu with SMT turned off.)

A 2400G is around 30W@3GHz, without SMT it will be at 22-23W@3GHz.

 

[NostaSeronx]

Well, as an XV fan it would be nice to believe, but I think Zen is highly efficient. Maybe the potential for FDX tricks you mentioned before (with voltage biasing) is so great that this could be overcome, so that XV+ could beat Zen in EPI?

It isn't so much XV, but more like a CMT version of Zen.

Each major Zen revision;
Zen -> Zen 2 -> Zen 5 is expecting >50% IPC boosts.

The opposite is for the mainstream core that replace Bristol/Stoney XV.
1 -> 2 -> 3 would be >50% EPC drops.

Like NTMBK says, the IO connections are the limit of how small you can make the die. For low powered small dies, SR is probably king for cheapest production cost small die. I don't think we've seen an AMD die in a while that's been well under 100mm2 (neither CPU nor GPU). So a good guess for that limit is ~100mm2.

22nm wouldn't seem much smaller. It could be the same die area and let you fit in a few more features. But how much more expensive is 22FDX over 28nm? If not much, I would think it'd be well worth it for the efficiency gains. Then the main question remains: can they justify the cost of the project for the sum of the expected future earnings from such a project?

I/O scales in FDSOI and the gate-first bulk diode also scale. So, I/O will shrink and be faster at more mature nodes. 22FDX can get the PCIE spec up to 56 GT/s for example.

Cost wise 22FDX and 22FDX+ both have lower cost than 28SHP/28A/28HPA. 22FDX is slightly below 28LPS(28nm PolySi not 28nm HKMG SLP) and 22FDX+ is potentially below 28SLP(28nm HKMG).
https://www.soitec.com/en/news/pres...o-long-term-supply-agreement-on-fd-soi-wafers
This agreements allows GlobalFoundries to buy FDSOI wafers at near bulk cost as long as demand sticks.

There are other factors: do they have spare staff or do they want to focus everything on radeon and zen? will the project compete with old stock inventory or is this not an issue?

AMD has been aware of GlobalFoundries' FDSOI plan since 2012. I would assume the architecture would be side-by-side based on the GlobalFoundries slides. What is in Zen will be ported across to the CMT core.

Zen -> 22FDX
Zen+ -> 22FDX+ Core1
Zen 2 -> 12FDX
Zen 3 -> 12FDX+ Core2
Zen 4?/5 -> 7FDX Core3
etc

Majority of the design would be 14LPPor12LPto22FDX+, etc. Mostly same front-end, mostly same back-end, and optimized mid/execution part for CMT. So, AMD will have a core optimized for benchmarks(Ryzen) and a core optimized for real workloads(mainstream core). While, mostly at the genetic/tile/macro/block level being the same design optimized for two different styles of the same workload.

 

[amd6502]

Cost wise 22FDX and 22FDX+ both have lower cost than 28SHP/28A/28HPA. 22FDX is slightly below 28LPS(28nm PolySi not 28nm HKMG SLP) and 22FDX+ is potentially below 28SLP(28nm HKMG).
https://www.soitec.com/en/news/pres...o-long-term-supply-agreement-on-fd-soi-wafers
This agreements allows GlobalFoundries to buy FDSOI wafers at near bulk cost as long as demand sticks. AMD has been aware of GlobalFoundries' FDSOI plan since 2012. I would assume the architecture would be side-by-side based on the GlobalFoundries slides. What is in Zen will be ported across to the CMT core.
.

Well, it seems hard to pass up such a cheap good process. I hope they put something out there.

I think the biggest advantage of CMT was design simplicity. But since Zen is already done (on amd64) that's no longer an advantage. (If they were to do a new core for a custom Risc-V or Acorn server APU then yes I would say CMT and reuse of XV and Zen components sounds great.)

Taking Zen parts and swapping SMT for CMT sounds like an intensive design. What do you think of just porting Stoney but with two extra threads (2+2 big.little) to keep it relevant for the next few years. One XV module, plus two Puma cores, with Puma's L2 serving also as L3 for the XV module. Perhaps add another CU to the iGPU if the 22nm density allows it to remain close to the desired minimum die area. Or, just taking Bristol Ridge and cutting down the iGPU to Stoney's size.

Meanwhile some good news, $199 Ataribox bottom end option looks likely. Wood grain edition is confirmed.

http://globenewswire.com/news-relea...tor-s-Edition-Onyx-Model-and-Accessories.html

https://www.zdnet.com/article/atari...nsole-gets-pre-order-date-199-starting-price/

https://www.pocket-lint.com/games/news/142369-atari-vcs-ataribox-pre-orders-price-specs-release-date

And some really long rants from bloggers:

https://www.youtube.com/watch?v=liugttMiBAA

https://www.youtube.com/watch?v=FwMD7NNRpP0

A 2400G is around 30W@3GHz, without SMT it will be at 22-23W@3GHz.

I think 8 threads/cores loaded on a well binned Piledriver FX 83xx is about 70W at 3GHz. So I'd call that a very good win for Zen with all threads loaded.

I don't know about excavator at 3 ghz. Guestimating 4 cores loaded at 3ghz might be 25W for well binned 28nm APU. (We know it's greater than 15W: http://www.cpu-world.com/CPUs/Bulldozer/AMD-A12-Series A12-9720P.html has base clock 2.7GHz with 15W TDP
and less than 35W: http://www.cpu-world.com/CPUs/Bulldozer/AMD-A12-Series PRO A12-9800E.html ; I'm not sure if some of that TDP power budget goes to the iGPU load; i think sustained full iGPU load at max GPU freq will eventually cut the CPU clockspeed below the base clock; i.e., "APU throttling")

Comparing to Abwx's 2400G with SMT off's ~22.5W the 14nm Zen again wins, especially considering that the IPC gain of Zen is >50%, and that Zen only needs to run at avg of 2GHz to keep up 3GHz excavator. (Also consider that 2GHz is near Zen's optimal perf/watt). So the question for AMD is to experiment with FDSOI or to just replace XV with a tiny die native dual core APU at 12nm or 14nm.

 

[dark zero]

At the end nosta, the 22 nm FDX will be used for Mediatek on their ARM A35 (or succesor) phone chips.... since 16 nm are still expensive and 12 nm are on their top tier chips.

 

[NostaSeronx]

Thee Final Stoney Ridge Refresh:
A9-9425
A6-9225
A4-9125

February 10, 2018 - May 12, 2018 for the laptops and AIO on Amazon. Which follows the 2017 Stoney Refresh 1.

I didn't even notice the launches in with the Ryzen chips in April; https://www.anandtech.com/show/12605/dells-8th-gen-alienware-laptops-and-monitors/7
(Bristol Ridge by Anandtech and Ryzen by Toms Hardware... what.... Stoney Ridge)

On the FDSOI side of things;
22FDX can be used for UHP(High-end) w/ Cortex A75 (w/ Meltdown/Spectre) or ULP(Low-end)/ULL(IoT) w/ Cortex A35. There is also a plethora of RISC-V IP on 22FDX as well.
(Mobility-22FDX range is Basic Smartphones(sub-$99) to Premium Tablets(>$499))

There is also a fast track HVM/Ramp-up for 12FDX by Q4 2018. With 12LP/14LPP products that are ported to 12FDX. The 12FDX port can have macro tiles that can be near 1:1 rather than somewhere 2:1. 22FDX <-> 12FDX is only a one key mistake, so 12LP Picasso and 12FDX Pre-Dali, would be synergistic.

 

[ao_ika_red]

There's no point buying Stoney Ridge-based laptop when you can get Ryzen 2200U laptop for less than $500 (at least in my country)

 

[dark zero]

So... Mediatek is gonna use the 22nm tech on their tablet processors?

They would use it easily that tech on their cheap tablets

 

[NostaSeronx]

There's no point buying Stoney Ridge-based laptop when you can get Ryzen 2200U laptop for less than $500 (at least in my country)

The A9-9425(Fan)/A9-9420e(Fanless)/A6-9225(Fan)/A6-9220e(Fanless)/A4-9125(Fan)/A4-9120e(Fanless) are aimed at this area; (all Stoney Ridge Refresh 2s)
• China skew
• Older
• More retired
• Lower income
-> Price more important than features.

So, the take away is that none of the machines should actually be beyond $300. A9-9425 Laptops with 1080p screens and a NVMe PCIe3.0-2x SSD should not exceed $350.
Price is 1st, then Resolution is 2nd, the Storage is 3rd in the market analysis.

Seems to me that the manufacturers are ballooning the cost before summer(late June) and back to school(early August) sales.

 

[ao_ika_red]

The A9-9425(Fan)/A9-9420e(Fanless)/A6-9225(Fan)/A6-9220e(Fanless)/A4-9125(Fan)/A4-9120e(Fanless) are aimed at this area; (all Stoney Ridge Refresh 2s)
• China skew
• Older
• More retired
• Lower income
-> Price more important than features.

So, the take away is that none of the machines should actually be beyond $300. A9-9425 Laptops with 1080p screens and a NVMe PCIe3.0-2x SSD should not exceed $350.
Price is 1st, then Resolution is 2nd, the Storage is 3rd in the market analysis.

Seems to me that the manufacturers are ballooning the cost before summer(late June) and back to school(early August) sales.

The problem is, most of Stoney-based laptop is priced almost the same with 2200u laptop.

 

[NostaSeronx]

The problem is, most of Stoney-based laptop is priced almost the same with 2200u laptop.

Yep, it makes no sense for the full ~124 mm squared A9-94xx that costs less than ~$30 per BGA(FT4) unit and less in bulk. To be price evaluated to a salvaged ~210 mm squared(Raven Ridge die) that costs less than ~$90 per BGA(FP5) unit and less in bulk.

- ~3x cheaper at SoC level
- FT4 for Refresh 2 utilizes the same VRM,Codec, etc motherboard IP as FP5.
- I don't get why the prices are so high.

 

[ao_ika_red]

Yep, it makes no sense for the full ~124 mm squared A9-94xx that costs less than ~$30 per BGA(FT4) unit and less in bulk. To be price evaluated to a salvaged ~210 mm squared(Raven Ridge die) that costs less than ~$90 per BGA(FP5) unit and less in bulk.

- ~3x cheaper at SoC level
- FT4 for Refresh 2 utilizes the same VRM,Codec, etc motherboard IP as FP5.
- I don't get why the prices are so high.

Something's odd with SR laptops. I actually almost offered SR latops to my family member, but because the price was very close to Skylake i3 laptops, in the end I offered them either Carrizo-L (Puma+) laptops or Skylake i3 laptops.

 

[NostaSeronx]

AMD has updated the marketing of Stoney Ridge and Bristol Ridge.

Stoney Ridge is a Low-End AP.
Bristol Ridge is a Mid-End AP.

Stoney Ridge Refresh 2 came out Q2 2018. If there is a Bristol Ridge Refresh 2 it will come out Q3 2018.

Now, GlobalFoundries has shifted and updated 22FDX/12FDX roadmaps.
-> 22FDX/22FDX+ is releasing with 7LP/7LP+ in 2019.
-> 12FDX/12FDX+ is releasing with 3LP/3LP+ in 2021.

Anything getting refreshed is definitely getting a 22FDX successor in 2019.

GlobalFoundries is licensing GAAE/GAAP from Samsung. (It might be more accurate to say Samsung and GlobalFoundries are licensing 3nm from IBM. Except, IBM doesn't own foundries and IBM specifically worked with Samsung.)

The important details is that 22FDX(+) achieves the typical and slow corners of 7LP. This is expected to follow the same with 12FDX for 3LP as well. The 12FDX(+) delay might imply that 12FDX might get UTBB Nanosheet transistor, aka Planar Nanosheet. Equivalent of FinFET to stacked Nanosheet, so UTBB FDSOI becomes UTBB Nanosheet.

 

[dark zero]

Bristol Ridge Refresh is not happening.

Heck, I see only AMD K12 using 22 nm.