AMD Bulldoozer going AVX.

[INOUTx64]

Originally posted by: Idontcare

Originally posted by: INOUTx64
My first post after 10 years of reading on this forum?
There is a discussion about this subject on this forum. According to that forum, AVX and AMD instructions are slightly different in OP codes

Welcome to the forums! :beer:

...

Thanks :beer:
I hope AMD can makes it successful than 3DNow! implementation. I remember buying k6-2 based on AMD's 3DNow! promise. I even tried hard to convert FPU instructions to 3DNow! instructions (disassemble -> convert -> patch) to get improved performance in applications. I admit, I had very little success on this. While this worked for tiny applications, slightly bigger application always crashed.

AMD documentation does not mention anything about extending existing SSE instruction to support 256bit, which Intel seems to support. Any thoughts ?

 

[Raqia]

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: jandlecack
I think the inclusion of AVX can only be beneficial for the chip, however, I'm burning to know how high the royalties are that Intel is getting for this.

In any case the Bulldozer chip archi is a promising one, and curiously the only one I'm even looking forward to. But last I heard it's projected to launch in 2010 or 2011.

@Gazelle: Please stop distracting from the point of this thread with every post you make.

What makes you think Intel will receive any royalties at all? Who would they receive the from and for what?

Presumably AVX is covered by Intel IP, and licensing it would involve some form of reciprocation by AMD to Intel's shareholders...otherwise someone is not carrying out their fiduciary responsibilities.

It begs the question - why does AMD seemingly always drag their feet when it comes to adopting/integrating/incorporating the latest ISA extensions of any and all sorts originated at Intel?

Every iteration of MMX, SSE, and AVX has been delayed intro on AMD chips (or in the case of AVX, wasn't planned at all but rather had a Bluray vs. HD-DVD showdown looming on the horizon)...and AMD's own attempts to put the cart before the horse (3DNow) weren't exactly the kinds of results one would think to be confidence building inside the circles of decision makers at AMD.

AMD64 is basically their one-time spot in the sun when it comes to ISA changes that successfully caused the tail to wag the dog, but this special occasion was created by microsoft and not the free markets where consumers decide which path becomes the new standard.

My assumption until now is that the reason AMD is basically always one step behind Intel on the ISA changes is because they are dragging their feet and prolonging the negotiation phase when it comes to the terms and conditions under which AMD licenses the IP incorporating the ISA extensions. It could be the other way around, Intel could be dragging their feet to intentionally delay AMD's ability to get products ready for market in the same timeframe...but one would think such a tactic in a two-company market such as this would arouse the interest of the DOJ as an abuse-of-monopoly tactic.

I'd imagine use of AVX is covered by their cross-licensing terms, which are under re-negotiation as we speak presumably.

 

[Idontcare]

Originally posted by: Raqia
I'd imagine use of AVX is covered by their cross-licensing terms, which are under re-negotiation as we speak presumably.

Don't forget that cross-licensing terms are NOT forward looking in terms of the specific IP which is cross-licensed, meaning they do not cover yet-to-be-created IP.

When Intel announces NEW IP, such as AVX, there is no cross-license agreement with AMD on that new IP until such time that an existing license is amended (requiring a re-negotiation process) or an wholly new license is created (also requiring a negotiation process).

Naturally we should assume that AMD's access to AVX is something that will be covered in any newly negotiated or renegotiated contracts, which will naturally involve reciprocation to Intel regarding their IP and their shareholder's equity.

AMD creating SSE5, and then offering to throw it away as a part of their reciprocation package for access to AVX would be a natural part of the process of IP leverage. There's nothing new under the sun here in this regard.

 

[aigomorla]

new instruction sets?

great... how long b4 it starts getting adapted?

i mean have you guys seen stuff for SSE4 even?

 

[Flipped Gazelle]

Originally posted by: aigomorla
new instruction sets?

great... how long b4 it starts getting adapted?

i mean have you guys seen stuff for SSE4 even?

Adobe products, and a lot of video software does.

 

[Idontcare]

Originally posted by: aigomorla
new instruction sets?

great... how long b4 it starts getting adapted?

i mean have you guys seen stuff for SSE4 even?

It does take a non-zero amount of time once a new ISA debuts until the software is available to take advantage of it.

There is no way around this as no software company is going to bother creating software programmed for a non-existent ISA.

It's not a chicken-versus-egg thing, the ISA simply MUST exist first before the software can exist.

The purpose of AMD and Intel creating bulletins and manuals on future ISA's like this is to reduce that timeline gap as much as possible. AV software products can start to preparing now to incorporate AVX-like instructions into products they intend to release in the circa 2010-2011 timeframe.

These things take years, and for good reason as it is extremely complicated and difficult work creating functional and worthwhile ISA extensions. If it wasn't complicated then we'd have seen FMA and AVX (along with SSE4.2 and earlier) all released and implemented on prior CPU's.

 

[iCyborg]

Originally posted by: aigomorla
new instruction sets?

great... how long b4 it starts getting adapted?

i mean have you guys seen stuff for SSE4 even?

I'd say it's used more than you think. E.g. one can do what my company does: simply use Intel IPP. It's a library optimized by Intel to use mmx/sse1-4 - from a user perspective it's just a bunch of DLLs/SOs and all you have to do is use it. Well, that and pay some money to Intel.
There probably are companies that would do it on their own via Intrinsics API or, God forbid, assembly, but I doubt many would find that cost effective compared to IPP. And from what I've noticed, Intel is pretty quick to utilize the new acrhitecture in their own software. It's in their interest after all.

 

[Phynaz]

Originally posted by: Idontcare

Originally posted by: aigomorla
new instruction sets?

great... how long b4 it starts getting adapted?

i mean have you guys seen stuff for SSE4 even?

It does take a non-zero amount of time once a new ISA debuts until the software is available to take advantage of it.

There is no way around this as no software company is going to bother creating software programmed for a non-existent ISA.

It's not a chicken-versus-egg thing, the ISA simply MUST exist first before the software can exist.

The purpose of AMD and Intel creating bulletins and manuals on future ISA's like this is to reduce that timeline gap as much as possible. AV software products can start to preparing now to incorporate AVX-like instructions into products they intend to release in the circa 2010-2011 timeframe.

These things take years, and for good reason as it is extremely complicated and difficult work creating functional and worthwhile ISA extensions. If it wasn't complicated then we'd have seen FMA and AVX (along with SSE4.2 and earlier) all released and implemented on prior CPU's.

The ISA specification must exist, but the actual cpu doesn't need to. The ISA can be emulated.

While not that many commercial applications would take this route, I believe the compiler writers may.

 

[Spoelie]

AMD and Intel have cross licensing agreements in place - any ISA extension determined by one can be used without royalties etc. by the other.

This allowed Intel in the past to implement their version of AMD64 and AMD to implement SSE without repercussions.

What AVX does in short, is reduce the amount of instructions needed to perform a given job. So given processors with the same efficiency (IPC) and the same clockspeed, the AVX processor would still need less time to complete a workload than the non-AVX processor, assuming the workload can make use of the new instructions.

Well that's how I understood it anyway.