We have already talked about AMD being a year behind Intel in process technology. How much would it matter in this category?
It has its pros and its cons. Being a year behind means that your critical decision points during development are also a year behind, which means you have the added advantage of the process hardware (tools, like immersion litho) being a year more mature or a year further along in their own development timeline so you have all the more data and confidence in your risk assessments when it comes time to make your decision regarding whether or not you are going to rely on those leading edge technologies when you enter your new node into production.
Immersion litho is a perfect example of this. The technology for making production-worthy immersion litho tools was maturing at a pace that was just too far behind Intel's own 45nm development schedule.
AMD's development schedule, by virtue of being about a year behind Intel's, was much better aligned with that of the toolset developer's schedule. As such, when it came time at AMD for the decision of whether to implement immersion-litho or double-patterning they had a year's more data on the production worthiness of immersion litho equipment and were able to assess the risk and make a data-driven decision to go for it.
This is just one example, but basically every process step in the entire flow benefits from similar advances in toolsets that are always going on. We just don't hear about them in the consumer world because not every process tool makes for a good PR story.
Is developing a "low leakage" version of an existing process harder or easier than advancing to the next node?
At TI we developed three flavors of a process node in parallel. Low-power/mobile, higher-power for plug-in devices, and then highest performance for CPU's.
You get to recycle your BEOL process tech (metal layers) but virtually the entire FEOL (transistor build) is developed around the targeted application. So the low-power transistors were independently developed/optimized/etc from the development efforts to make the high-power xtors, and so on.
The differences are not so simple as just changing gate-oxide. All the implants are adjusted, all the spacers and physical dimensions are adjusted. Min Lg will be larger, EOT will be thicker, etc. Pretty much everything is altered and optimized to minimize power-consumption for the targeted parametrics excepting for the minimum gate pitch.
In other words it is very much like developing a wholely new node, takes nearly as much time, and as such is done in parallel. Intel's low-power stuff coming out a year after the high-power doesn't mean they started the low-power development when the high-power was done...they probably spent a minimum of 3yrs developing that low-power flavor of their node. (at TI we called these different flavors of a node the "sub-nodes")
And it is the lead times that are involved here that makes the situation pretty much as it is. You need 3 yrs to develop the low-power stuff, the chip designers need at least 2yrs for simple DSP stuff, longer if it is a complicated SOC design like Atom or Llano. You can't just tell everyone to wait it out to the next next node. The treadmill is always going and you can't really jump ahead in an effective manner.