AMD's 65nm process was just... bad. below 90nm smaller transistors are not necessarily more efficient. i think that was a major setback for barcelona aside from the tlb bug.That's not what I'm talking about though.
Look at Fermi... on the GTX465, they turn pretty much half the GPU off... yea, it's still fully operational, but the power consumption and clockspeed scaling are horrible. It's just too large for the 40 nm process. The dies are so large that there will always be poor areas on the die (not just cache obviously). Then it all just drops off exponentially.
AMD had a similar situation with their 65 nm process. Even their dualcores were initially having trouble beating the 90 nm ones.
Cutting down die size and/or using MCM could have benefited Barcelona on 65 nm considerably, no doubt in my mind.
Eventually 45 nm solved the problems.
AMD's 65nm process was just... bad.
kind of like the process advantage that amd has over nvidia
So you're saying you didn't know how many cores Barcelona has? And I had to explain that to you?
No, I wanted to make them look exactly as bad as the benchmark data indicates.
From the article you linked yourself:
"AMD's native quad-core needs about 76ns to exchange (L1) cache information. That's not bad, but it's not fantastic either as the shared L2 cache approach of the Xeons allows the dual cores to exchange information via the L2 in about 26-30ns. Once you need to get information from core 0 to core 3, the dual die CPU of Intel still doesn't need much more time (77ns) than the quad-core Opteron (76ns). The complex L1-L2-L3 hierarchy might negate the advantages of being a "native" quad-core somewhat, but we have to study this a bit further as it is quite a complex matter."
Half the latency? Hardly.
And you want to accuse ME of poor form?
You can figure out the objective results yourself.
See the above quote from the article. Intel's L2 cache gives you 26-30 ns core-to-core, almost a factor 3 better than AMD.
So where is the advantage of the L3 cache and the native quad core design? We're not seeing it.
And as you can see, the dual core Opteron actually did BETTER, both with on-die and socket-to-socket communication.
I made that very clear: It is a native dualcore design that DOES take advantage of the single-die design. It serves as a reference for the gains you can get in core-to-core communications.
That wasn't apparent in your reply at all.
You needed to demonstrate a passing knowledge of the fact that the chip was, in fact, not a K8, which your snide remark did not indicate. It was almost as if you really believed that Barcelona was the same speed as a K8.
How is that? AMD outsources its GPU and chipset production to TSMC, just like nVidia.
nVidia has the advantage at TSMC because they place bigger orders and get lower pricing.
i'm sure you guys are very entertained by having a pointless (in terms of anyone actually convincing eachother) argument over k10 architecture, but you've made a very interesting thread about 32nm/llano/orochi into a not-so-interesting thread about chest-pounding and intellectual superiority.
..bla blah freaking bla..
Anyone remember Virgin Cola's attempt? They actually did carry it at my local grocery for a time.It's a fact of life, but why is that a problem?
I mean, there's Pepsi and Coca Cola aswell, but it's virtually impossible for a third party to take a significant share of the worldwide cola/soft drink market. Again, barrier of entry and level of risk for setting up a worldwide operation on such a large scale makes it impossible.
Anyone remember Virgin Cola's attempt? They actually did carry it at my local grocery for a time.
For an 'entirely new' architecture, I think 15% is not impressive (especially not if you factor in that clockspeeds went DOWN by about 15% if not more).
Conroe vs Presler was much bigger than that, and Nehalem vs Penryn aswell (without sacrificing any clockspeed at all).
If Bulldozer is again an 'entirely new' architecture, giving an 'impressive' boost of 15% per clock over Phenom... well, Intel will really be sweating, won't they?
And the SINGLE BIGGEST reason for that problem is that the die was too large. Had they gone MCM rather than single-die, or had they removed the L3 cache and relied on the HT bus only, they could probably have scaled the clockspeed considerably.
That's what I've been driving at.
It just didn't work on 65 nm. They had to wait for 45 nm to get it going.
Intel had shared cache before AMD did, and did it better too.
And Intel was actually smart enough to use an MCM approach for 65 nm quadcores, which greatly improved yields and therefore clockspeeds/performance/power consumption.
AMD didn't have MCM technology yet.
K10 was not designed for 65nm. It was originally planned for 45nm release...
And who the heck are you?
I'm sure you guys are very entertained by having a pointless (in terms of anyone actually convincing eachother) argument over K10 architecture, but you've made a very interesting thread about 32nm/Llano/Orochi into a not-so-interesting thread about chest-pounding and intellectual superiority.
exactly !!
If you two don't stop, i am going to lock this thread, and give you both infractions
markfw900
anandtech moderator
Where K10 missed the mark imo was clockspeed and thermals.
As for the shared cache, Intel had a shared L2, AMD had a shared L3 first.
For starters, the massive amounts of L3 cache found in Tulsa cores are shared between both cores. Each CPU has an independent L2 cache still. AMD revealed earlier this year that K8L will also use the same ideology, with independent L2 and shared L3 cache. Intel has had shared L3 cache on its Itanium 2 server lineup for years, but this is the first time such a feature has appeared on x86.
This new shared cache has several advantages -- each CPU core can use the L3 cache without sending a request back to the system I/O redundantly. In order to manage errors in the cache, Intel has technology that already exists on Itantium 2, dubbed Pellston. Intel has incorporated this onto Tulsa but renamed the technology to CST, or Cache Safe Technology.
Where K10 missed the mark imo was clockspeed and thermals.
This, plus the dreaded TLB bug.
let's face it, there are 2 reasons that intel is kicking amd's ass right now.
1. their cpu's clock higher and
2. their cpu's are better clock/clock
if bulldozer fixes both of these issues for amd then they will be on top again. if they fix one of these issues then at least they'll be better off than they are now, and then we can look at other factors like total power draw, performance/watt, etc. If they can't get either of them then they may as well just call it phenom 2.5 and call it a day.
(In the multi-core era) I would imagine it is possible for AMD to beat Intel on the single threaded performance through design. Enough cores on a larger process vs Intel's ability to multiply cores on its much smaller process.
How important is absolute single threaded performance in the server market? Or is "good enough" performance per watt a better idea most of the time?
It really depends on what the server is supposed to do.How important is absolute single threaded performance in the server market? Or is "good enough" performance per watt a better idea most of the time?
AMD seems to struggle every other process tech generation. Last time the problem occured at 0.13u.
It really depends on what the server is supposed to do.
There are servers that continually handle thread after thread after thread with very little need for actual single-threaded efficiency. OLTP servers are mostly like this. Here, the more cores, the better - for example, Apache/Mongrel/Tomcat + PHP/Python/Perl/Ruby/Java, and using a database almost purely as a datastore. Some implementations of Lotus Notes can be seen that way as well, especially if a lot of the processing is done client-side.
Then there are servers that not only serve multiple users/clients, but also need to process tons of data to generate complex reports. Here, single-threaded performance is as critical as having as many cores as possible, because each request can require a good chunk of processing power. Any web-based, or client-server type system qualifies as long as it contains a big database and produces meaningful reports of any sort. LAMP stack systems and Lotus Notes implementation with no LN clients installed (clients connect through the browser), for example, can easily demand high single-threaded performance, especially when deployed in large enterprises. You just don't want to see an Atom-level server (even 512 Atoms in a box like SeaMicro) execute a multi-join query on tables with millions of rows, loop through the results, and make one or a few more queries for each result retrieved from the original multi-join query, plus a few more math operations on the data.
Sometimes, a server may only need "occasional" single-threaded throughput. For example, most of the time it acts as a simple OLTP, but then every morning it is expected to perform a batch job that requires much computational power, and it has to end before the daily transactions start. In such a case, SeaMicro type solutions may not be feasible if you want to just have one server for the job, and the batch job cannot be parallelized. Similarly, we can also concoct a use-case where SeaMicro types would be perfect or perfectly acceptable. It just depends on the requirements, and just how critical or time-constrained the batch job is.
EDIT:
As for "performance per watt" - this is sometimes misleading. If the server demands high single-threaded performance as in examples above, then a CPU with better performance per watt on paper may not give better power savings in the real world, especially if the advantage on paper comes at the cost of performance. Johan covered this in his latest article. The faster processor can finish a job faster and then return to low-power/power-saving mode faster than the "energy efficient"/"low-power" processor. When this scenario happens often, there is little to no power savings gained from going "low-power"/"energy-efficient", and you have inconvenienced the clients/users by making them wait longer for their report to finish.