AMD Carrizo APU Details Leaked

[mrmt]

The Tegra sales boom in the Tegra 3 generation had nothing to do with the use of a low power companion core. Rather, they were first to market with quad-core CPU in the ultra mobile space, and they also secured the original Nexus 7 design win. Tegra 4 was delayed by quite a few months which led to the sales dip, but the quad-core Cortex A15 was and is very competitive with quad-core Krait 400.

The companion core is exactly one of the things that makes Tegra handicapped when competing against Krait. Tegra isn't competitive on costs and perf/watt is inferior to Krait.

 

[ams23]

The companion core is exactly one of the things that makes Tegra handicapped when competing against Krait. Tegra isn't competitive on costs and perf/watt is inferior to Krait.

No it's not. That makes zero sense whatsoever. The companion core is only used in scenarios that are not very processor intensive (such as standby, basic video and music playback, etc). The perf. per watt and perf. per mm^2 is likely to be very similar between Krait 400 and Cortex A15. The upcoming Cortex A15 R3 variant reportedly has superior perf. per watt and perf. per mm^2 compared to Krait 400 used in Snapdragon S800: http://cdn.pcper.com/files/imagecache/article_max_width/review/2014-01-05/slides03.jpg

 

[positivedoppler]

I clicked on a thread expecting to read about carrizo, instead its about apple, intel nvidia, arm and pretty much everything else =\

 

[mrmt]

No it's not. That makes zero sense whatsoever. The companion core is only used in scenarios that are not very processor intensive (such as standby, basic video and music playback, etc). The perf. per watt and perf. per mm^2 is likely to be very similar between Krait 400 and Cortex A15. The upcoming Cortex A15 R3 variant reportedly has superior perf. per watt and perf. per mm^2 compared to Krait 400 used in Snapdragon S800: http://cdn.pcper.com/files/imagecache/article_max_width/review/2014-01-05/slides03.jpg

You are committing the same mistake as fjodor, taking only the workloads where the little core excels while you should be taking the performance of the entire SoC at every performance point.

Upcoming A15 R3 doesn't help much, Qualcomm is on its way to launch its A53 derivative.

 

[witeken]

Witeken, don't fool yourself about "three orders of magnitude". I have a Haswell tablet and it's a very nice device, but it runs pretty hot sometimes; this isn't a 7W part, despite the "SDP" marketing. As for the 130W parts, they have considerably higher core counts to spread that TDP between- 8 for the Haswell E parts, up to 14 for their workstation counterparts. A single Haswell core doesn't go above ~30W I expect, even with Turbo enabled, unless you start heavily overclocking it. That's roughly an order of magnitude that it scales over, same as any other processor core.

Fair enough. I generally agree with you, but I'd like to clarify myself. I didn't say 3 orders of magnitude is possible, I don't know if that's true. I said almost 2 orders of magnitude. You shouldn't look at TDPs alone. Intel surely is able to release a 200W part with a frequency of 3.6GHz+ instead of ~2.7GHz, just like they could also release a ~1GHz dualcore.

But my point is that Intel doesn't only go for highest possible performance, but also for great performance/watt, scalability and dynamic range. And with every die shrink the DR increases.

(reply to your last sentence But why does ARM have like 4 different architectures to cover far less than 1 order of magnitude?

 

[sm625]

big.LITTLE hasnt even worked right so far. Samsung has just now gotten it working at least somewhat reasonably. But it is still handicapped by technology. What it really needs is nonvolatile caches. If the little core has even a small bit of nonvolatile memory, then it can simply be turned off at any moment. It's TDP can be set to effectively any value. Data can be copied to and from it to the big cores as needed. But right now it is simply too much trouble to move all that data around and still gain any performance. The R&D is better spent elsewhere, for example in simply making the single big core be able to power on and off as fast as possible.

 

[witeken]

I clicked on a thread expecting to read about carrizo, instead its about apple, intel nvidia, arm and pretty much everything else =\

I don't want to read the whole thread again but looking from page 6-7 on when this discussion began, I guess it started about IPC gains, power consumption and die sizes. Continuing with some Skylake and compute discussion, and a discussion about 2x256bit vs. 4x128bit. Finishing off with the current discussion about BIG.little, power consumption of architectures, R&D, scaling (especially after this comment),... after some guy asked about integrating arm cores in AMD.

To be honest, I like and enjoy reading them. Instead of this being just about Carrizo (or the main subject of any thread), when something related to it is posted, why restrict yourself to it if there can be a very interesting discussion instead which evolves naturally over time. I guess it's quite rare that you actually don't see that happen.

 

[DrMrLordX]

I clicked on a thread expecting to read about carrizo, instead its about apple, intel nvidia, arm and pretty much everything else =\

There is some information about it earlier on in the thread. I sort of tried to steer it back on-topic but failed. But hey, we're looking at a Q1 or H1 2015 release, so we should get concrete information on it in about a year. I think it will be an interesting chip if/when HSA support becomes more widespread.

 

[Blitzvogel]

I think Apple really got it right with sticking to 2 good cores with high performance FPU in their last two SoCs. A cellphone or tablet isn't a machine for work, so all that general data management and manipulation required for practical applications and heavy multitasking isn't a necessity. It's a media machine that needs alot of decode and media (visual, sound, games) capability where the focus is on one main application being used at a time with a few idling in the background. Because of this focus, Apple can score big where it counts while having room for such a great graphics array. Apple probably saves quite a bit of time on the integration of SoC component design. It's like trying to cram four 15,000 lb thrust engines + a 10,000 HP turboprop for cruise on a fighter plane instead of just sticking to a couple 25,000 lb thrust engines. You'll lose out on total max thrust, but you will make vast reductions in weight, drag, and all the extra integrations required like extra fuel lines, wiring, etc.


So, big.LITTLE is just a waste to me.

Anyone who knows me would not be surprised by my analogy :awe:

 

[NostaSeronx]

So apparently GCN2 is not a new ISA but a different structure of units.

Kaveri(Steamroller)/GCN1(with the VI ISA)
to
Carrizo(Excavator)/GCN2(with the VI ISA)
to
Basilisk(Post-Excavator)/GCN2(with the PI ISA)

 

[inf64]

So apparently GCN2 is not a new ISA but a different structure of units.

Kaveri(Steamroller)/GCN1(with the VI ISA)
to
Carrizo(Excavator)/GCN2(with the VI ISA)
to
Basilisk(Post-Excavator)/GCN2(with the PI ISA)

Basilisk is cancelled and was not an APU project but a Steamroller based server part/FX part. Basilisk equivalent on APU side is Kaveri, which already launched.

Gecko(8 module huge chip?) was to be a server part/FX part based on Excavator core but that one is ditched also. APU equivalent is already known to be Carrizo. Excavator is supposed to bring more threads per module capability, some form of CMT/SMT hybrid (although Bulldozer already has it since FP unit is SMT) - so 4 threads per dual "core" module. Oh and AVX2+BMI2 capability.

 

[NostaSeronx]

Basilisk is cancelled and was not an APU project but a Steamroller based server part/FX part. Basilisk equivalent on APU side is Kaveri, which already launched.

Basilisk is a SoC project that is meant to be after Carrizo. One of the big features for Basilisk is the use of Ceramic/Glass based TSV.

Gecko(8 module huge chip?) was to be a server part/FX part based on Excavator core but that one is ditched also.

40h-4Fh is the model coming after the 02h Warsaw. If it follows the path of Orochi, it will be named after a diety/god/demi-god. Mostly with something related to 16 since Orochi was related to the number 8.

APU equivalent is already known to be Carrizo. Excavator is supposed to bring more threads per module capability, some form of CMT/SMT hybrid (although Bulldozer already has it since FP unit is SMT) - so 4 threads per dual "core" module. Oh and AVX2+BMI2 capability.

bdver4 can support these extensions based on its generation;
sha avx512pf avx512f avx512er avx512cd xsaveopt xsave rtm fxsr bmi2 avx2 rdrnd

There is no sign that the Excavator module will have more threads than a Steamroller module.

 

[norseamd]

40h-4Fh is the model coming after the 02h Warsaw. If it follows the path of Orochi, it will be named after a diety/god/demi-god. Mostly with something related to 16 since Orochi was related to the number 8.

they are making a 32 core or 16 module cpu?

 

[NostaSeronx]

they are making a 32 core or 16 module cpu?

Orochi(00h-02h) = 4 modules that have 8 cores.
40h-4Fh = 8 modules that have 16 cores.

 

[norseamd]

Orochi = 4 module with 8 cores. 40h-4Fh = 8 modules with 16 cores.

thought they already had some sort of 8 module server processor?

 

[NostaSeronx]

thought they already had some sort of 8 module server processor?

It uses a multi-chip module.

You have two 00h/02h model chips that use the same package. It isn't a monolithic 8 module chip but instead a dual 4 module chip. While 40h-4Fh model chips are a single 8 module chip.

 

[jpiniero]

It uses a multi-chip module.

You have two 00h/02h model chips that use the same package. It isn't a monolithic 8 module chip but instead a dual 4 module chip. While 40h-4Fh model chips are a single 8 module chip.

When do you think this is coming out? AMD's own roadmaps only show Warsaw until the end of 2015.

 

[NostaSeronx]

When do you think this is coming out?

Any time after Q2 2015 for the server market. While for the enthusiast market, anytime after E3 2014.

 

[jpiniero]

Any time after Q2 2015 for the server market. While for the enthusiast market, anytime after E3 2014.

That just seems unrealistic, esp at 28 nm. The 4 module die is big enough as it is.

 

[inf64]

Well you can make up stuff all day long, I just told you what the situation is .

 

[NostaSeronx]

That just seems unrealistic, esp at 28 nm. The 4 module die is big enough as it is.

630 mm² - MCM Orochi 32nm.
482 mm² - 2 Orochi 2.5D 28nm.
409 mm² - 2 Orochi 2.5D HDL 28nm.

http://i.imgur.com/hOphMuH.jpg

29.47 mm² * 8 = 235.76 mm²

16 MB of L3;
10.86 mm² * 8 = 86.88 mm²
or
13 mm² * 8 = 104 mm²

Quad DDR4;
32 mm²

236 + 104 + 32 = 372

I would round it in between 380 mm² to 410 mm² just to be safe if it is using Steamroller. That is implying that it is also on the same 28nm SHP process as Kaveri.

 

[Homeles]

Sounds expensive.

 

[NostaSeronx]

Sounds expensive.

It would be no more expensive than Centurian or Warsaw, for both enthusiast and server markets.

Server 40h models will be less than 100 watts. Following the footsteps of Warsaw in that market; efficiency and cheapness is king. Enthusiast 40h models will be less than 220 watts. In the enthusiast market it will be 40h models that could not achieve a certain server bin.

Server 40h => High quality bins/HQ ASIC. (high efficiency; poor overclocking)
Enthusiast 40h = Low quality bins/LQ ASIC. (high performance; good enough overclocking)

^-- We won't get such huge shifts between the same model with Carrizo and Toronto.

 

[norseamd]

what socket would these 8 module enthusiast cpus work

 

[NostaSeronx]

what socket would these 8 module enthusiast cpus work

LGA for Enthusiast/Server and BGA for Dense Server.

Much like Carrizo and Toronto;
FM2p/FM3 for Carrzio-DT <-- LGA Desktop
FP4 for Carrizo-MT <-- BGA Mobile
SP2 for Toronto-DS <-- BGA Server