I did some research and if Excavator is using High Density Libraries. It is impossible to get higher performance with a node lesser than 28-nm SHP.
The only three nodes, I consider to be better than 28-nm SHP;
28-nm FDSOI
20-nm Low Power Manufacturing
14-nm FDSOI
AMD has stated they achieved 30% area density and 30% lower total power consumption. The performance loss is not linear, my estimations are ~40%.
Excavator with a "bulk" node less than TSMC 28-nm HP and GlobalFoundries 28-nm SHP. Would need to see a performance increase architecturally if not frequency of....
~40%(high density cell libraries) + ~15%(lesser node) + ~30%(slide says Excavator performs this much better).
That is a total of an ~85% barrier wall of performance to improve. That points to Excavator incapable of being faster with bulk.
With 28-nm FDSOI;
~40%(high density cell libraries) - 40%(high performance(FBB+Poly Biasing) 28nm FDSOI node(1.2V-1.3V Vdd)) + ~30%(slide says Excavator performs this much better).
Bringing down the architectural improvement to just 30%.
With FDSOI there is an area shrink and a leakage drop at high performance-ended designs. The lower leakage would allow the designs to have higher frequencies at lower TDPs. FDSOI doesn't need a large architectural improvement.
Also, for the IVR, 28-nm FDSOI supports the same Switched Capacitors(iVRMs) from POWER8. You want to know why that is important? Well if you check IBM's research on switch capacitors you will find it is closed-loop.
Dynamic voltage and frequency scaling (DVFS) techniques—along with associated techniques
such as dynamic voltage scaling (DVS) and adaptive voltage and frequency scaling (AVFS)—
are very effective in reducing power, since lowering the voltage has a squared effect on active
power consumption. DVFS techniques provide ways to reduce power consumption of chips on
the fly by scaling down the voltage (and frequency) based on the targeted performance
requirements of the application. Since DVFS optimizes both the frequency and the voltage, it
is one of the only techniques that is highly effective on both dynamic and static power.
Dynamic voltage scaling is a subset of DVFS that dynamically scales down the voltage (only)
based on the performance requirements. Adaptive voltage and frequency scaling is an
extension of DVFS. In DVFS, the voltage levels of the targeted power domains are scaled in
fixed discrete voltage steps. Frequency-based voltage tables typically determine the voltage
levels. It is an open-loop (no feedback) system with large margins built in, and therefore the
power reduction is not optimal. On the other hand, AVFS deploys closed-loop voltage scaling
and is compensated for variations in temperature, process, and V=IR drop using dedicated
circuitry (typically analog in nature) that constantly monitors performance and provides active
feedback. Although the control is more complex, the payoff in terms of power reduction is
higher.
Analog in FDSOI(& PDSOI?) is superior than analog in bulk and FinFETs.
That IVR is positioned pretty close to;
GlobalFoundries committed to using ST’s FD-SOI tech for 28nm and 20nm production in 2012, and expects to put it into volume production by the end of this year, for 28nm and 14nm processes. In May, STMicroelectronics announced that Samsung would use ST’s 28nm FD-SOI tech for foundry customers. Samsung plans to offer the process in early 2015.