AMD Carrizo Pre-release thread

[mrmt]

Please don't post guesses as if they were fact.

(Though I agree with your guess.)

Thanks

 

[Enigmoid]

A wide core but needless to say a wide core will stomp all over Intel's design. Some 120 million startup blew away Intel's Haswell IPC already. More transistors poured into a wider core rather than a longer core payed off. (though no x86 backward compatibility tardiness they had to deal with)

Yeah It's probably more memory IO. Not really sure though.

Taking VISC at face value? On a CPU operating and designed for 350 mhz?

Perhaps you should wait and see.

 

[maarten12100]

Taking VISC at face value? On a CPU operating and designed for 350 mhz?

Perhaps you should wait and see.

Just saying the approach in which cores could scale as if they were running essentially a gpu is a big thing. If they get it to work and all.

 

[el etro]

3.5Ghz at 35W is a killer deal for notebooks, but not a good deal in the desktops. Sadly, the newer tech nodes don't focus more on high performance processors but only low power, low frequency processors.
Low power process the bleeding edge tablet SOCs are made are already reaching 80% of the clockspeeds of the Notebook high performance CPUs(base clocks for all cores), and High-Performance nodes are becoming less and less optimized for the bigger power targets(See the differences between TSMC28SHP process and GF14nmLPP process). Moar Corez will be the solution for HPC/Server workloads. The Desktop market will forcedly follow this trend, since it will never dies, but it will have to change.
With all of this trends following, High Density Libraries can be a very good deal for AMD architectures in the future.



The death of the High-Clocked processors and of the High-Clocked High Performance Desktop Processors(E.G. 95W and 125W 4GHZ processors) is closer. PC market will obviously follow this trend.

 

[Enigmoid]

3.5Ghz at 35W is a killer deal for notebooks, but not a good deal in the desktops. Sadly, the newer tech nodes don't focus more on high performance processors but only low power, low frequency processors.
Low power process the bleeding edge tablet SOCs are made are already reaching 80% of the clockspeeds of the Notebook high performance CPUs(base clocks for all cores), and High-Performance nodes are becoming less and less optimized for the bigger power targets(See the differences between TSMC28SHP process and GF14nmLPP process). Moar Corez will be the solution for HPC/Server workloads. The Desktop market will forcedly follow this trend, since it will never dies, but it will have to change.
With all of this trends following, High Density Libraries can be a very good deal for AMD architectures in the future.

Sadly this (for both AMD and intel) don't matter. What matters is the attainable speed on mobile. You can have a 3.5 ghz turbo but if you never turbo that high.......

 

[el etro]

Sadly this (for both AMD and intel) don't matter. What matters is the attainable speed on mobile. You can have a 3.5 ghz turbo but if you never turbo that high.......

Who knows it now? What if the processor can turbo to 3.5? The Kaveri 4C/35W TDP has already a 2.7GHZ baseclock.


Go see the fastest HSW mobile Core i7 available: It goes up to 4GHZ turbo(1 core)!

 

[Shehriazad]

All this talk about turbo frequencies n stuff...but don't the frequencies get hit hard by the use of AMDs high density libraries?

I wouldn't expect the chip to turbo to 3.5 at such low wattage.

 

[el etro]

All this talk about turbo frequencies n stuff...but don't the frequencies get hit hard by the use of AMDs high density libraries?

I wouldn't expect the chip to turbo to 3.5 at such low wattage.

Still can get there, and IPC improvements will be there too. GF28nmSHP is more matured at this time, yields are on the sky, process can be milked more.
Remember even Kaveri A10-7800 had to be launched months later than A10-7850 due to lack of process improvement. Peak frequency can be a problem, but the improvements on power using still will help even more to the processor operates to its limits:

http://wccftech.com/amd-talks-power-efficient-design-chips-carrizo-apu-double-efficiecy-kaveri-apu/

The Kaveri chip already haves a 2.7GHz base clock.

http://www.notebookcheck.net/AMD-Kaveri-FX-7600P-Notebook-Processor.117329.0.html

High Density Libraries can make a effect on Power Budget of the processor:

The methodology comes from AMD’s work in designing graphics cores, and we’ve already seen some of it used in AMD’s ‘cat cores (e.g. Bobcat). As an example, AMD demonstrated a 30% reduction in area and power consumption when these new automated procedures with high density libraries were applied to a 32nm Bulldozer FPU:

The tradeoff is peak frequency. These heavily automated designs won’t be able to clock as high as the older hand drawn designs. AMD believes the sacrifice is worth it however because in power constrained environments (e.g. a notebook) you won’t hit max frequency regardless, and you’ll instead see a 15 - 30% energy reduction per operation. AMD equates this with the power savings you’d get from a full process node improvement.

And more advanced power saving and power management IC technologies going on(Some of them are already on Nvidia Maxwell and many of them are on Intel Broadwell):

At the end, Shehriazad, the Carrizo game is not provide a new level of performance to its APUs, but instead is to provide the performance of the top-bin Kaveri APUs to the Top-Dog Carrizo mobile APU.

 

[Abwx]

Sustainable I don't know but there is this:

I see no reason for it not to go up to 3.5GHz. I'm quite positive Carrizo won't even take a performance hit just like with Kaveri I think there will be an upper range for efficiency of 3GHz but at the same time if you push enough voltage and keep the die cool 5GHz could be doable. (not talking extreme cooling just water cooling or decent air)

It should go to 3.5 without any problem, there would be no point in releasing less performing APUs at a 35W TDP, but here we have people explaining us that AMD made all thoses efforts to get back to Llano level of performance, current mobile 35W Kaveri FX7600P base frequency is 2.7 and turbo is 3.6.

The chip can be extended to 65W if AMD want to do so, there s no technical reason that would point to this being not possible, quite the contrary.

 

[mrmt]

Who knows it now? What if the processor can turbo to 3.5? The Kaveri 4C/35W TDP has already a 2.7GHZ baseclock.

3.5Ghz is the base clock of the 65W A-10 7800. To expect clocks around 3.5Ghz at 35W with Carrizo on the same node is hoping for a miracle.

 

[jpiniero]

3.5Ghz is the base clock of the 65W A-10 7800. To expect clocks around 3.5Ghz at 35W with Carrizo on the same node is hoping for a miracle.

I don't think anyone has suggested that the base clock would be 3.5 Ghz, only turbo. And that is in question for sure because of HDL.

 

[mrmt]

I don't think anyone has suggested that the base clock would be 3.5 Ghz, only turbo. And that is in question for sure because of HDL.

Don't forget that the 35W also includes the PCH. I think 35W is already next to the limits of usable bins when using HDL. We might see Carrizo clocks stable or with a slight reduction at 15W when compared to Kaveri, 35W Carrizo should have a sizable reduction in terms of both base clock and turbo.

 

[el etro]

3.5Ghz is the base clock of the 65W A-10 7800. To expect clocks around 3.5Ghz at 35W with Carrizo on the same node is hoping for a miracle.

The tradeoff is peak frequency. These heavily automated designs won’t be able to clock as high as the older hand drawn designs. AMD believes the sacrifice is worth it however because in power constrained environments (e.g. a notebook) you won’t hit max frequency regardless, and you’ll instead see a 15 - 30% energy reduction per operation. AMD equates this with the power savings you’d get from a full process node improvement./QUOTE]

 

[mrmt]

The tradeoff is peak frequency. These heavily automated designs won’t be able to clock as high as the older hand drawn designs. AMD believes the sacrifice is worth it however because in power constrained environments (e.g. a notebook) you won’t hit max frequency regardless, and you’ll instead see a 15 - 30% energy reduction per operation. AMD equates this with the power savings you’d get from a full process node improvement./QUOTE]

Read this statement again and see if you can fit a close to 100% perf/watt improvement + PCH power consumption on this budget. Because this is exactly what you are suggesting here.

 

[el etro]

Read this statement again and see if you can fit a close to 100% perf/watt improvement + PCH power consumption on this budget. Because this is exactly what you are suggesting here.

100% perf/watt no, i guess 40%, is like a node jump. Sufficient to make Top-End Carrizo performs like the 65W A10-7800. This is my guess.

 

[mrmt]

100% perf/watt no, i guess 40%, is like a node jump. Sufficient to make Top-End Carrizo performs like the 65W A10-7800. This is my guess.

And how a 40% power consumption improvement can make a 35W chip + PCH clock as high as a 65W chip?

 

[Idontcare]

The tradeoff is peak frequency. These heavily automated designs won’t be able to clock as high as the older hand drawn designs. AMD believes the sacrifice is worth it however because in power constrained environments (e.g. a notebook) you won’t hit max frequency regardless, and you’ll instead see a 15 - 30% energy reduction per operation. AMD equates this with the power savings you’d get from a full process node improvement./QUOTE]

Resonant mesh was hyped as delivering similar power savings, but reality showed up and it was rather meh. I'm not putting much faith into AMD's claims of a "full process node improvement" until we see the chips tested by third party reviewers.

 

[cbn]

If the High density cell library is, in fact, equal to a full node improvement (or something close to it) wouldn't AMD have announced a large die server part using Excavator by now?

 

[Arachnotronic]

Resonant mesh was hyped as delivering similar power savings, but reality showed up and it was rather meh. I'm not putting much faith into AMD's claims of a "full process node improvement" until we see the chips tested by third party reviewers.

Did resonant mesh ever even show up?

 

[el etro]

Resonant mesh was hyped as delivering similar power savings, but reality showed up and it was rather meh. I'm not putting much faith into AMD's claims of a "full process node improvement" until we see the chips tested by third party reviewers.

It did some little improvement on Richland, no?

RCM was so "godly" like this when announced by AMD?

If the High density cell library is, in fact, equal to a full node improvement (or something close to it) wouldn't AMD have announced a large die server part using Excavator by now?

My guess is they're cutting off every R&D resources(and every single waste of money they can cut) they can to focus in Zen/K12. Even with a "full node improvement" the XV Opteron would lack IPC to fight against big Xeon on the server market. A 18C36T 22nm Xeon would likely crush a 16C(They don't have any research on Moar Corez now) XV Opteron.

AMD don't talk publicly, but they surely want to get rid of Bulldozer as soon as they can.

 

[geoxile]

Resonant mesh was hyped as delivering similar power savings, but reality showed up and it was rather meh. I'm not putting much faith into AMD's claims of a "full process node improvement" until we see the chips tested by third party reviewers.

No, RCM was never "hyped" because they quantified the improvement.

http://www.extremetech.com/computin...esonant-clock-mesh-to-push-trinity-above-4ghz

Cyclos claims that using its technology can cut total IC power by up to 10%.

While the result varied on the workload it seemed like RCM did help the Piledriver refresh

http://www.tomshardware.com/reviews/a10-6700-a10-6800k-richland-review,3528-11.html

 

[geoxile]

Read this statement again and see if you can fit a close to 100% perf/watt improvement + PCH power consumption on this budget. Because this is exactly what you are suggesting here.

PCH? You mean the FCH (Fusion Controller Hub aka the Southbridge)? It will be integrated onto the die, and I highly doubt the TDP is not inclusive of the full die.

 

[Abwx]

PCH? You mean the FCH (Fusion Controller Hub aka the Southbridge)? It will be integrated onto the die, and I highly doubt the TDP is not inclusive of the full die.

PCH is a cut down version with 2 sata, 2 usb3 and 4 usb2, its TDP should be about 2W at most when fully loaded, wich rarely happen, the impact with normal use should be about 0.2-0.3W IIRC AMD s numbers.

Also they said that the cores will consume 40% less, that is 66% better perf/watt at the cores level, this allow 30-35% higher frequency at same cores power dissipation, this correlate well with their claim of 30% higher perfs at 15W TDP compared with Kaveri, so unless there s a 30% higher IPC, wich is unlikely, they ll have forcibly to raise the frequency to get thoses 30%, if there s no IPC improvements they would had to clock the thing at 3.5 to get the claimed improvement, this sound too high for a 3.5 base frequency at 35W TDP, so they probably had to increase IPC to bridge the gap.

 

[AtenRa]

Dont forget Carrizo uses a different 28nm process than Kaveri. Kaveri used GloFo 28SHP where Carrizo is using a more like 28SOC process with different interconnects that is more closely to Beema/Mullins.

Combine that with HDL, Excavator CPU Cores, new iGPU architecture (probably Tonga based) and integrated FCH, and mobile Carrizo will have the highest perf/watt and/or power reduction of AMDs mobile APUs today. That is why AMD is talking like having a new process effect.

 

[NTMBK]

When adding in the TDP of the FCH, remember the power savings from integration. There is no off-chip communication between the two chips, which will reduce the power consumption of both and make a more efficient platform.