Not only that, the integrated FCH is of the same low power process as the rest of the APU, unlike before when they used older process for the FCH chipset.
When adding in the TDP of the FCH, remember the power savings from integration. There is no off-chip communication between the two chips, which will reduce the power consumption of both and make a more efficient platform.
Dont forget Carrizo uses a different 28nm process than Kaveri. Kaveri used GloFo 28SHP where Carrizo is using a more like 28SOC process with different interconnects that is more closely to Beema/Mullins.
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Platform improvements, yes, but you are throwing all the power consumption to the SoC, so there will be a performance hit to it.When adding in the TDP of the FCH, remember the power savings from integration. There is no off-chip communication between the two chips, which will reduce the power consumption of both and make a more efficient platform.
Die area will be sacrificed to the fch. The question is how much. We know that the Bolton south bridge was on 65nm. But this isn't Bolton it is something with reduced specs. It will be more like a half Bolton to begin with at 65nm. I have a Kaveri FX-7500 based Lenovo notebook here and saw the chipset. It is a rather tiny chip 5x8mm meaning 40mm^2 or so. I expect the die shrunk version with half the capabilities to take no more than 20mm^2 of the Carrizo die. Probably less historically speaking:Platform improvements, yes, but you are throwing all the power consumption to the SoC, so there will be a performance hit to it.
a 8W discrete gpuThat slide is so massively misleading.
a 8W discrete gpu
But the point is the chipset on die will be smaller not only due to it being cut down and shrunk. But also the fact that it can share some already exiting things on the apu and the interconnect is no longer needed.
Yeah as I said the Carrizo die will have space dedicated to that part. But it will lead to a reduction in how much space the chipset would take up. Due to it being integrated, shrunk and cutdown.Chipset on die makes it bigger. And you increase power consumption for the die. The only place you save is platform size and platform power.
The sole reason why everything wasnt integrated already was due to those 2 constraints.
Chipset on die makes it bigger. And you increase power consumption for the die. The only place you save is platform size and platform power.
The sole reason why everything wasnt integrated already was due to those 2 constraints.
Platform improvements, yes, but you are throwing all the power consumption to the SoC, so there will be a performance hit to it.
I'm pretty sure that this is MORE than enough. Cache is also down to 1MB per core if I remember correctly? (unless that has changed again)
The amount of free space is ridiculous.
Its new Excavator core is 23% smaller and uses 40% less power than AMD’s previous x86 core.
I don't see how lower performance is wishful thinking. Everything points to Carrizo being amazing in terms of efficiency doing away with the problems Kaveri had. One thing that will remain is the relatively low IPC.2 USB3, 2 SATA and 8 USB2 in Kabini, this take 10-14mm2 and they surely use this existing fch design to reduce RD cost and time to market, L2 cache has been halved compared to Kaveri to make room for the enhancements.
Not only what you wrote does mean nothing but i also would be very concerned if i was you, they ll get 30% higher perfs at same TDP despite integrating the FCH wich can use as much as 13-14% of the SoC power within a 15W TDP APU, there will be no performance hit, numbers published say that perfs will be 30% higher, you just expressed wishfull thoughts that are busted anyway by the available infos.
Also cores are quite smaller area wise, reduction in size has been published by AMD.
I don't see how lower performance is wishful thinking. Everything points to Carrizo being amazing in terms of efficiency doing away with the problems Kaveri had. One thing that will remain is the relatively low IPC.
I can't wait for February but I'm still disappointed that there are no benches out yet. CES was a total bust.
PCH is a cut down version with 2 sata, 2 usb3 and 4 usb2, its TDP should be about 2W at most when fully loaded, wich rarely happen, the impact with normal use should be about 0.2-0.3W IIRC AMD s numbers.
2 USB 2.0 along 2 USB 3.0 port would work for the consumer. Actually the average consumer doesn't even care as long as it works. (with ok speeds)2 USB 3.0 and 2 Sata ports are already putting Carrizio solely in the mobile/ low end desktop market. Can't have SSD, HDD, and OD. Two USB 3.0 ports is cutting it (other reports say 4 which is sufficient).
Carrizo will be AMDs first APU to implement a full Fusion Control Hub (FCH) what we used to call a south bridge on-die, but its doing so at some cost to overall features. The FCH will be a stripped-down variant, with two SATA 6G ports, four USB 3.0 ports, and four USB 2.0 ports. This will only apply to mobile variants drop a Carrizo APU into the FM2+ socket, and the onboard FCH will disable itself while the motherboard FCH takes over.
2 USB 3.0 and 2 Sata ports are already putting Carrizio solely in the mobile/ low end desktop market. Can't have SSD, HDD, and OD. Two USB 3.0 ports is cutting it (other reports say 4 which is sufficient).
And I really don't doubt that those chipset parts made in 28nm are going to be suuuper tiny on the chip...don't most mainboards generally have way bigger formats? (like 40nm and above)
Intels PCH is made on 32nm for example. If I recall right AMDs FCH is as well.
Platform improvements, yes, but you are throwing all the power consumption to the SoC, so there will be a performance hit to it.
Intels PCH is made on 32nm for example. If I recall right AMDs FCH is as well.
(useless to say it is useless to have that many USB ports) :whiste:
This is where extremetech got their source so Mobile Carrizo will have up to 4 USB 3.0 and 4 USB 2.0 port. (useless to say it is useless to have that many USB ports) :whiste:
Tom's was allowed to see 3 systems and positive impressions thus far:
http://www.tomshardware.com/news/amd-carrizo-carrizo-l-notebook-apu,28345.html
I didn't know that so much for sophisticated board layout that was talked up by board designers. (still 500H work in a board I give them that )Not really. USB is used to connect devices within the laptop, not just add external ports- the webcam, trackpad, keyboard will probably all use USB, and potentially things like an SD card reader too (though they might be connected by PCIe). I know on some supercheap craptops, even ethernet adapters are attached internally by USB!
The slide is pretty old. Still it had all the other things correct and AMD had this same slide design leak with Kaveri.Where's the hardware H.265 decode on this slide...? Did AMD do the hybrid GPU decode thing and claim that it was done "in hardware" or is this slide just really old?
AMD FCH like A85X and A88X are made at 65nm.
Also, only Broadwell PCH is made at 32nm. Older chipsets are made with 45nm.